
# This file is used by the simulation model as well as the ispLEVER bitstream
# generation process to automatically initialize the PCS quad to the mode
# selected in the IPexpress. This file is expected to be modified by the
# end user to adjust the PCS quad to the final design requirements.
# channel_0 is in "PCI Express" mode
# channel_1 is in "PCI Express" mode
# channel_2 is in "PCI Express" mode
# channel_3 is in "PCI Express" mode

ch0 13 03  # Powerup Channel
ch0 00 01
ch1 13 03  # Powerup Channel
ch1 00 01
ch2 13 03  # Powerup Channel
ch2 00 01
ch3 13 03  # Powerup Channel
ch3 00 01
quad 28 50  # Reference clock multiplier
quad 29 10  # FPGA sourced refclk
# quad 02 00  # ref_pclk source is ch0
quad 18 04  # PCI Express x4 Mode
quad 14 7F  # Word Alignment Mask
quad 15 03  # +ve K
quad 16 7C  # -ve K
# quad 0D 97  # Watermark level on CTC
quad 0E 00  # insertion/deletion control of CTC
quad 12 1C  # pattern for CTC match
quad 13 01
quad 19 40  # MCA x4 alignment
quad 01 FF  # MCA mclk select to ch0
# quad 04 00  # MCA enable 4 channels via ports
quad 05 01  # MCA latency
quad 06 06  # MCA depth
# quad 07 FF  # MCA alignment mask
quad 08 BC  # MCA alignment character
quad 09 BC  # MCA alignment character
# quad 0A 15  # MCA k control
quad 01 FF  # Ch3 as MCA clock source
quad 02 30  # Ch3 as ref_p clock source
quad 30 04  # Set TX Sync Bit
ch0 15 10  # +6dB equalization
ch1 15 10  # +6dB equalization
ch2 15 10  # +6dB equalization
ch3 15 10  # +6dB equalization
ch0 14 93  # pre
ch1 14 93
ch2 14 93
ch3 14 93
quad 41 00  # de-assert serdes_rst



