Project Settings
Project Name | proj_1 | Device Name | impl_1: Lattice LAV-AT : LAV_AT_X70
Implementation Name | impl_1 | Top Module | blink_top
Pipelining | 1 | Retiming | 0
Resource Sharing | 1 | Fanout Guide | 1000
Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0
Clock Conversion | 0 | FSM Compiler | 1
Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
(compiler) | Complete | 139 | 13 | 0 | - | 00m:03s | - | 2/19/2024 9:55 AM
(premap) | Complete | 17 | 2 | 0 | 0m:01s | 0m:01s | 189MB | 2/19/2024 9:56 AM
(fpga_mapper) | Complete | 19 | 18 | 0 | 0m:03s | 0m:03s | 295MB | 2/19/2024 9:56 AM
Multi-srs Generator | Complete |  |  |  |  |  |  | 2/19/2024 9:56 AM
Area Summary
Register bits | 32 | I/O cells | 16
Block RAMs (v_ram) | 0 | LUTs (total_luts) | 47
Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
blink_top|un1_seg21_inferred_clock | 200.0 MHz | NA | NA
pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock | 200.0 MHz | 184.0 MHz | -0.434
System | 200.0 MHz | NA | 5.000
Optimizations Summary
Combined Clock Conversion | 1 / 1 |  |