@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: MO111 :"d:\avant_versa_revb\avant-x versa board revb_blink\pll_h\rtl\pll_h.v":359:23:359:34|Tristate driver apb_prdata_o_1 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_1 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\avant_versa_revb\avant-x versa board revb_blink\pll_h\rtl\pll_h.v":359:23:359:34|Tristate driver apb_prdata_o_2 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_2 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\avant_versa_revb\avant-x versa board revb_blink\pll_h\rtl\pll_h.v":359:23:359:34|Tristate driver apb_prdata_o_3 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_3 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\avant_versa_revb\avant-x versa board revb_blink\pll_h\rtl\pll_h.v":359:23:359:34|Tristate driver apb_prdata_o_4 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_4 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\avant_versa_revb\avant-x versa board revb_blink\pll_h\rtl\pll_h.v":359:23:359:34|Tristate driver apb_prdata_o_5 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_5 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\avant_versa_revb\avant-x versa board revb_blink\pll_h\rtl\pll_h.v":359:23:359:34|Tristate driver apb_prdata_o_6 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_6 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\avant_versa_revb\avant-x versa board revb_blink\pll_h\rtl\pll_h.v":359:23:359:34|Tristate driver apb_prdata_o_7 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_7 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\avant_versa_revb\avant-x versa board revb_blink\pll_h\rtl\pll_h.v":359:23:359:34|Tristate driver apb_prdata_o_8 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_8 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\avant_versa_revb\avant-x versa board revb_blink\pll_h\rtl\pll_h.v":359:23:359:34|Tristate driver apb_prdata_o_9 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_9 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\avant_versa_revb\avant-x versa board revb_blink\pll_h\rtl\pll_h.v":359:23:359:34|Tristate driver apb_prdata_o_10 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_10 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
