`

    #Build: Synplify Pro (R) U-2023.03LR-SP1, Build 214R, Oct 17 2023
    #install: D:\radiant\2024.1\synpbase
    #OS: Windows 10 or later
    #Hostname: LSHITD0127

    # Mon Feb 19 09:55:55 2024

    #Implementation: impl_1

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-SP1
    Install: D:\radiant\2024.1\synpbase
    OS: Windows 10 or later
    Hostname: LSHITD0127

    Implementation : impl_1
    Synopsys HDL Compiler, Version comp202303synp1, Build 218R, Built Oct 17 2023 09:25:20, @

    @N: :  | Running in 64-bit mode
    ###########################################################[

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-SP1
    Install: D:\radiant\2024.1\synpbase
    OS: Windows 10 or later
    Hostname: LSHITD0127

    Implementation : impl_1
    Synopsys VHDL Compiler, Version comp202303synp1, Build 218R, Built Oct 17 2023 09:25:20, @

    @N: :  | Running in 64-bit mode
    @N: :  | Can't find top module!
    Top entity isn't set yet!
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\radiant\2024.1\ip\pmi\pmi_lav-at.vhd'.
    VHDL syntax check successful!

    At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 87MB peak: 88MB)

    Process completed successfully.
    # Mon Feb 19 09:55:57 2024

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-SP1
    Install: D:\radiant\2024.1\synpbase
    OS: Windows 10 or later
    Hostname: LSHITD0127

    Implementation : impl_1
    Synopsys Verilog Compiler, Version comp202303synp1, Build 218R, Built Oct 17 2023 09:25:20, @

    @N: :  | Running in 64-bit mode
    @I::"D:\radiant\2024.1\synpbase\lib\generic\lav-atx.v" (library work)
    @I::"D:\radiant\2024.1\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"D:\radiant\2024.1\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"D:\radiant\2024.1\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_addsub.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_addsub.v":"D:\radiant\2024.1\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v" (library work)
    @N:CG334 : lscc_add_sub.v(313) | Read directive translate_off.
    @N:CG333 : lscc_add_sub.v(333) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_add.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_add.v":"D:\radiant\2024.1\ip\pmi\../common/adder/rtl\lscc_adder.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_complex_mult.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_complex_mult.v":"D:\radiant\2024.1\ip\pmi\../common/complex_mult/rtl\lscc_complex_mult.v" (library work)
    @N:CG334 : pmi_complex_mult.v(92) | Read directive translate_off.
    @N:CG333 : pmi_complex_mult.v(101) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_counter.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_counter.v":"D:\radiant\2024.1\ip\pmi\../common/counter/rtl\lscc_cntr.v" (library work)
    @N:CG334 : lscc_cntr.v(129) | Read directive translate_off.
    @N:CG333 : lscc_cntr.v(143) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_distributed_dpram.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_distributed_dpram.v":"D:\radiant\2024.1\ip\pmi\../common/distributed_dpram/rtl\lscc_distributed_dpram.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_distributed_spram.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_distributed_spram.v":"D:\radiant\2024.1\ip\pmi\../common/distributed_spram/rtl\lscc_distributed_spram.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_distributed_rom.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_distributed_rom.v":"D:\radiant\2024.1\ip\pmi\../common/distributed_rom/rtl\lscc_distributed_rom.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_distributed_shift_reg.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_distributed_shift_reg.v":"D:\radiant\2024.1\ip\pmi\../common/ram_shift_reg/rtl\lscc_shift_register.v" (library work)
    @N:CG334 : pmi_distributed_shift_reg.v(126) | Read directive translate_off.
    @N:CG333 : pmi_distributed_shift_reg.v(135) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_fifo.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_fifo.v":"D:\radiant\2024.1\ip\pmi\../avant/fifo/rtl\lscc_fifo.v" (library work)
    @N:CG334 : lscc_fifo.v(3267) | Read directive translate_off.
    @N:CG333 : lscc_fifo.v(3274) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_fifo_dc.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_fifo_dc.v":"D:\radiant\2024.1\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v" (library work)
    @N:CG334 : lscc_fifo_dc.v(4910) | Read directive translate_off.
    @N:CG333 : lscc_fifo_dc.v(4914) | Read directive translate_on.
    @N:CG334 : lscc_fifo_dc.v(4945) | Read directive translate_off.
    @N:CG333 : lscc_fifo_dc.v(4949) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_mac.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_mac.v":"D:\radiant\2024.1\ip\pmi\../common/mult_accumulate/rtl\lscc_mult_accumulate.v" (library work)
    @N:CG334 : pmi_mac.v(94) | Read directive translate_off.
    @N:CG333 : pmi_mac.v(109) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_multaddsubsum.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_multaddsubsum.v":"D:\radiant\2024.1\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v" (library work)
    @N:CG334 : lscc_mult_add_sub_sum.v(210) | Read directive translate_off.
    @N:CG333 : lscc_mult_add_sub_sum.v(227) | Read directive translate_on.
    @N:CG334 : pmi_multaddsubsum.v(84) | Read directive translate_off.
    @N:CG333 : pmi_multaddsubsum.v(93) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_multaddsub.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_multaddsub.v":"D:\radiant\2024.1\ip\pmi\../common/mult_add_sub/rtl\lscc_mult_add_sub.v" (library work)
    @N:CG334 : pmi_multaddsub.v(91) | Read directive translate_off.
    @N:CG333 : pmi_multaddsub.v(100) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_mult.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_mult.v":"D:\radiant\2024.1\ip\pmi\../common/multiplier/rtl\lscc_multiplier.v" (library work)
    @N:CG334 : pmi_mult.v(87) | Read directive translate_off.
    @N:CG333 : pmi_mult.v(96) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_ram_dp.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_ram_dp.v":"D:\radiant\2024.1\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v" (library work)
    @N:CG334 : lscc_ram_dp.v(1060) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp.v(1064) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp.v(1095) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp.v(1099) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_ram_dp_be.v" (library work)
    @N:CG334 : pmi_ram_dp_be.v(146) | Read directive translate_off.
    @N:CG333 : pmi_ram_dp_be.v(155) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_ram_dp_true.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_ram_dp_true.v":"D:\radiant\2024.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v" (library work)
    @N:CG334 : lscc_ram_dp_true.v(1880) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(1885) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(1916) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(1920) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(1953) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(1958) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(1988) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(1992) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(2508) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(2513) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(2544) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(2548) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(2581) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(2586) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(2617) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(2621) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(3108) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(3113) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(3144) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(3148) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(3181) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(3186) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(3217) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(3221) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_ram_dq.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_ram_dq.v":"D:\radiant\2024.1\ip\pmi\../avant/ram_dq/rtl\lscc_ram_dq.v" (library work)
    @N:CG334 : lscc_ram_dq.v(1485) | Read directive translate_off.
    @N:CG333 : lscc_ram_dq.v(1491) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_ram_dq_be.v" (library work)
    @N:CG334 : pmi_ram_dq_be.v(87) | Read directive translate_off.
    @N:CG333 : pmi_ram_dq_be.v(95) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_rom.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_rom.v":"D:\radiant\2024.1\ip\pmi\../avant/rom/rtl\lscc_rom.v" (library work)
    @N:CG334 : lscc_rom.v(970) | Read directive translate_off.
    @N:CG333 : lscc_rom.v(976) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_sub.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_sub.v":"D:\radiant\2024.1\ip\pmi\../common/subtractor/rtl\lscc_subtractor.v" (library work)
    @I::"D:\Avant_Versa_RevB\Avant-X Versa Board revB_Blink\source\impl_1\blink_top.v" (library work)
    @I::"D:\Avant_Versa_RevB\Avant-X Versa Board revB_Blink\pll_H\rtl\pll_H.v" (library work)
    Verilog syntax check successful!

    At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB)

    Process completed successfully.
    # Mon Feb 19 09:55:57 2024

    ###########################################################]
    ###########################################################[
    @I::"D:\radiant\2024.1\synpbase\lib\generic\lav-atx.v" (library work)
    @I::"D:\radiant\2024.1\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"D:\radiant\2024.1\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"D:\radiant\2024.1\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_addsub.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_addsub.v":"D:\radiant\2024.1\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v" (library work)
    @N:CG334 : lscc_add_sub.v(313) | Read directive translate_off.
    @N:CG333 : lscc_add_sub.v(333) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_add.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_add.v":"D:\radiant\2024.1\ip\pmi\../common/adder/rtl\lscc_adder.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_complex_mult.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_complex_mult.v":"D:\radiant\2024.1\ip\pmi\../common/complex_mult/rtl\lscc_complex_mult.v" (library work)
    @N:CG334 : pmi_complex_mult.v(92) | Read directive translate_off.
    @N:CG333 : pmi_complex_mult.v(101) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_counter.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_counter.v":"D:\radiant\2024.1\ip\pmi\../common/counter/rtl\lscc_cntr.v" (library work)
    @N:CG334 : lscc_cntr.v(129) | Read directive translate_off.
    @N:CG333 : lscc_cntr.v(143) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_distributed_dpram.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_distributed_dpram.v":"D:\radiant\2024.1\ip\pmi\../common/distributed_dpram/rtl\lscc_distributed_dpram.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_distributed_spram.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_distributed_spram.v":"D:\radiant\2024.1\ip\pmi\../common/distributed_spram/rtl\lscc_distributed_spram.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_distributed_rom.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_distributed_rom.v":"D:\radiant\2024.1\ip\pmi\../common/distributed_rom/rtl\lscc_distributed_rom.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_distributed_shift_reg.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_distributed_shift_reg.v":"D:\radiant\2024.1\ip\pmi\../common/ram_shift_reg/rtl\lscc_shift_register.v" (library work)
    @N:CG334 : pmi_distributed_shift_reg.v(126) | Read directive translate_off.
    @N:CG333 : pmi_distributed_shift_reg.v(135) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_fifo.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_fifo.v":"D:\radiant\2024.1\ip\pmi\../avant/fifo/rtl\lscc_fifo.v" (library work)
    @N:CG334 : lscc_fifo.v(3267) | Read directive translate_off.
    @N:CG333 : lscc_fifo.v(3274) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_fifo_dc.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_fifo_dc.v":"D:\radiant\2024.1\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v" (library work)
    @N:CG334 : lscc_fifo_dc.v(4910) | Read directive translate_off.
    @N:CG333 : lscc_fifo_dc.v(4914) | Read directive translate_on.
    @N:CG334 : lscc_fifo_dc.v(4945) | Read directive translate_off.
    @N:CG333 : lscc_fifo_dc.v(4949) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_mac.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_mac.v":"D:\radiant\2024.1\ip\pmi\../common/mult_accumulate/rtl\lscc_mult_accumulate.v" (library work)
    @N:CG334 : pmi_mac.v(94) | Read directive translate_off.
    @N:CG333 : pmi_mac.v(109) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_multaddsubsum.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_multaddsubsum.v":"D:\radiant\2024.1\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v" (library work)
    @N:CG334 : lscc_mult_add_sub_sum.v(210) | Read directive translate_off.
    @N:CG333 : lscc_mult_add_sub_sum.v(227) | Read directive translate_on.
    @N:CG334 : pmi_multaddsubsum.v(84) | Read directive translate_off.
    @N:CG333 : pmi_multaddsubsum.v(93) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_multaddsub.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_multaddsub.v":"D:\radiant\2024.1\ip\pmi\../common/mult_add_sub/rtl\lscc_mult_add_sub.v" (library work)
    @N:CG334 : pmi_multaddsub.v(91) | Read directive translate_off.
    @N:CG333 : pmi_multaddsub.v(100) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_mult.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_mult.v":"D:\radiant\2024.1\ip\pmi\../common/multiplier/rtl\lscc_multiplier.v" (library work)
    @N:CG334 : pmi_mult.v(87) | Read directive translate_off.
    @N:CG333 : pmi_mult.v(96) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_ram_dp.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_ram_dp.v":"D:\radiant\2024.1\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v" (library work)
    @N:CG334 : lscc_ram_dp.v(1060) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp.v(1064) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp.v(1095) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp.v(1099) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_ram_dp_be.v" (library work)
    @N:CG334 : pmi_ram_dp_be.v(146) | Read directive translate_off.
    @N:CG333 : pmi_ram_dp_be.v(155) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_ram_dp_true.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_ram_dp_true.v":"D:\radiant\2024.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v" (library work)
    @N:CG334 : lscc_ram_dp_true.v(1880) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(1885) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(1916) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(1920) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(1953) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(1958) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(1988) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(1992) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(2508) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(2513) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(2544) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(2548) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(2581) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(2586) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(2617) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(2621) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(3108) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(3113) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(3144) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(3148) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(3181) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(3186) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(3217) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(3221) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_ram_dq.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_ram_dq.v":"D:\radiant\2024.1\ip\pmi\../avant/ram_dq/rtl\lscc_ram_dq.v" (library work)
    @N:CG334 : lscc_ram_dq.v(1485) | Read directive translate_off.
    @N:CG333 : lscc_ram_dq.v(1491) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_ram_dq_be.v" (library work)
    @N:CG334 : pmi_ram_dq_be.v(87) | Read directive translate_off.
    @N:CG333 : pmi_ram_dq_be.v(95) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_rom.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_rom.v":"D:\radiant\2024.1\ip\pmi\../avant/rom/rtl\lscc_rom.v" (library work)
    @N:CG334 : lscc_rom.v(970) | Read directive translate_off.
    @N:CG333 : lscc_rom.v(976) | Read directive translate_on.
    @I:"D:\radiant\2024.1\ip\pmi\pmi_lav-at.v":"D:\radiant\2024.1\ip\pmi\pmi_sub.v" (library work)
    @I:"D:\radiant\2024.1\ip\pmi\pmi_sub.v":"D:\radiant\2024.1\ip\pmi\../common/subtractor/rtl\lscc_subtractor.v" (library work)
    @I::"D:\Avant_Versa_RevB\Avant-X Versa Board revB_Blink\source\impl_1\blink_top.v" (library work)
    @I::"D:\Avant_Versa_RevB\Avant-X Versa Board revB_Blink\pll_H\rtl\pll_H.v" (library work)
    Verilog syntax check successful!
    @N:CG364 : pll_H.v(198) | Synthesizing module pll_H_ipgen_lscc_pll in library work.

    	VCO_FREQ=88'b0011010000110000001100000011000000101110001100000011000000110000001100000011000000110000
    	REFCLK_FREQ=80'b00110001001100000011000000101110001100000011000000110000001100000011000000110000
    	REFCLK_SEL=32'b00000000000000000000000000000000
    	FBKSEL_CLKOUT=32'b00000000000000000000000000000000
    	EXT_FBK_DELAY=32'b00000000000000000000000000000011
    	USE_ECLK_FBPATH=32'b00000000000000000000000000000000
    	EN_USR_FBKCLK=32'b00000000000000000000000000000000
    	EN_EXT_CLKDIV=32'b00000000000000000000000000000001
    	EN_SYNC_CLK0=32'b00000000000000000000000000000000
    	EN_FAST_LOCK=32'b00000000000000000000000000000000
    	EN_LOCK_DETECT=32'b00000000000000000000000000000001
    	EN_PLL_RST=32'b00000000000000000000000000000001
    	EN_CLK0_OUT=32'b00000000000000000000000000000001
    	EN_CLK1_OUT=32'b00000000000000000000000000000000
    	EN_CLK2_OUT=32'b00000000000000000000000000000000
    	EN_CLK3_OUT=32'b00000000000000000000000000000000
    	EN_CLK4_OUT=32'b00000000000000000000000000000000
    	EN_CLK5_OUT=32'b00000000000000000000000000000000
    	EN_CLK6_OUT=32'b00000000000000000000000000000000
    	EN_CLK7_OUT=32'b00000000000000000000000000000000
    	EN_CLK0_CLKEN=32'b00000000000000000000000000000000
    	EN_CLK1_CLKEN=32'b00000000000000000000000000000000
    	EN_CLK2_CLKEN=32'b00000000000000000000000000000000
    	EN_CLK3_CLKEN=32'b00000000000000000000000000000000
    	EN_CLK4_CLKEN=32'b00000000000000000000000000000000
    	EN_CLK5_CLKEN=32'b00000000000000000000000000000000
    	EN_CLK6_CLKEN=32'b00000000000000000000000000000000
    	EN_CLK7_CLKEN=32'b00000000000000000000000000000000
    	CLK0_BYP=32'b00000000000000000000000000000000
    	CLK1_BYP=32'b00000000000000000000000000000000
    	CLK2_BYP=32'b00000000000000000000000000000000
    	CLK3_BYP=32'b00000000000000000000000000000000
    	CLK4_BYP=32'b00000000000000000000000000000000
    	CLK5_BYP=32'b00000000000000000000000000000000
    	CLK6_BYP=32'b00000000000000000000000000000000
    	CLK7_BYP=32'b00000000000000000000000000000000
    	PHASE_SHIFT_TYPE=32'b00000000000000000000000000000000
    	CLK0_PHI=32'b00000000000000000000000000000001
    	CLK1_PHI=32'b00000000000000000000000000000001
    	CLK2_PHI=32'b00000000000000000000000000000001
    	CLK3_PHI=32'b00000000000000000000000000000001
    	CLK4_PHI=32'b00000000000000000000000000000001
    	CLK5_PHI=32'b00000000000000000000000000000001
    	CLK6_PHI=32'b00000000000000000000000000000001
    	CLK7_PHI=32'b00000000000000000000000000000001
    	CLK0_DEL=32'b00000000000000000000000010100000
    	CLK1_DEL=32'b00000000000000000000000000000001
    	CLK2_DEL=32'b00000000000000000000000000000001
    	CLK3_DEL=32'b00000000000000000000000000000001
    	CLK4_DEL=32'b00000000000000000000000000000001
    	CLK5_DEL=32'b00000000000000000000000000000001
    	CLK6_DEL=32'b00000000000000000000000000000001
    	CLK7_DEL=32'b00000000000000000000000000000001
    	PLL_SSEN=32'b00000000000000000000000000000000
    	PLL_DITHEN=32'b00000000000000000000000000000001
    	PLL_ENSAT=32'b00000000000000000000000000000001
    	PLL_INTFBK=32'b00000000000000000000000000000001
    	PLL_CLKR=6'b000000
    	PLL_CLKF=26'b00000010100000000000000000
    	PLL_CLKV=26'b00000000000000000000000000
    	PLL_CLKS=12'b000000000000
    	PLL_BWADJ=12'b000000010011
    	PLL_CLKOD0=11'b00010011111
    	PLL_CLKOD1=11'b00000000000
    	PLL_CLKOD2=11'b00000000000
    	PLL_CLKOD3=11'b00000000000
    	PLL_CLKOD4=11'b00000000000
    	PLL_CLKOD5=11'b00000000000
    	PLL_CLKOD6=11'b00000000000
    	PLL_CLKOD7=11'b00000010011
    	REG_INTERFACE=32'b01001110011011110110111001100101
    	WAIT_FOR_LOCK=32'b00000000000000000000000000000001
    	DEVICE_NAME=80'b01001100010000010101011000101101010000010101010000101101010110000011011100110000
    	SIMULATION=32'b00000000000000000000000000000000
    	REFCLK_DIV=32'b00000000000000000000000000000001
    	FBK_INTG_DIV=12'b000000101000
    	FBK_FRAC_DIV=8'b00000000
    	FBK_FRAC_SSC=6'b000000
    	FBK_FRAC_14B=14'b00000000000000
    	BWADJ_DIV=32'b00000000000000000000000000010100
    	CLK0_DIV=32'b00000000000000000000000010100000
    	CLK1_DIV=32'b00000000000000000000000000000001
    	CLK2_DIV=32'b00000000000000000000000000000001
    	CLK3_DIV=32'b00000000000000000000000000000001
    	CLK4_DIV=32'b00000000000000000000000000000001
    	CLK5_DIV=32'b00000000000000000000000000000001
    	CLK6_DIV=32'b00000000000000000000000000000001
    	CLK7_DIV=32'b00000000000000000000000000010100
    	FVCO=80'b00000000000000000000000000000000000000000000000000110100001100000011000000110000
    	FCLKI=80'b00000000000000000000000000000000000000000000000000000000001100010011000000110000
    	CLKI_DIV=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	CLKI_SEL=56'b01010010010001010100011001001101010101010101100000110000
    	CLKFB_DIV=80'b00000000000000000000000000000000000000000000000000000000000000000011010000110000
    	CLKFB_PATH=104'b00000000000000000000000000000000000000000100100101001110010101000100010101010010010011100100000101001100
    	FRACTIONAL_FBK=128'b00110000011000100011000000110000001100000011000000110000001100000011000000110000001100000011000000110000001100000011000000110000
    	EXT_FB_DELAY=32'b00110000011000100011000100110001
    	LOOP_BW=112'b0011000001100010001100000011000000110000001100000011000000110000001100000011000100110000001100000011000100110001
    	CLKV_SSC_SLOPE=224'b00110000011000100011000000110000001100000011000000110000001100000011000000110000001100000011000000110000001100000011000000110000001100000011000000110000001100000011000000110000001100000011000000110000001100000011000000110000
    	CLKS_SSC_RATE=112'b0011000001100010001100000011000000110000001100000011000000110000001100000011000000110000001100000011000000110000
    	CLKOP_DIV=80'b00000000000000000000000000000000000000000000000000000000001100010011011000110000
    	CLKOS_DIV=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	CLKOS2_DIV=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	CLKOS3_DIV=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	CLKOS4_DIV=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	CLKOS5_DIV=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	CLKPHY_DIV=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	INT_CLK7_DIV=80'b00000000000000000000000000000000000000000000000000000000000000000011001000110000
    	INT_CLKOD0_DIV=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	INT_CLKOD1_DIV=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	INT_CLKOD2_DIV=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	INT_CLKOD3_DIV=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	INT_CLKOD4_DIV=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	INT_CLKOD5_DIV=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	INT_CLKOD6_DIV=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	INT_CLKOD7_DIV=80'b00000000000000000000000000000000000000000000000000000000000000000011001000110000
    	CLKOP_OUT_SEL=32'b01000100010010010101011001000001
    	CLKOS_OUT_SEL=32'b01000100010010010101011001000010
    	CLKOS2_OUT_SEL=32'b01000100010010010101011001000011
    	CLKOS3_OUT_SEL=32'b01000100010010010101011001000100
    	CLKOS4_OUT_SEL=32'b01000100010010010101011001000101
    	CLKOS5_OUT_SEL=32'b01000100010010010101011001000110
    	CLKPHY_OUT_SEL=48'b010001000100100101010110010100000100100001011001
    	TEST_CLK7_OUT_SEL=32'b01000100010010010101011000110111
    	SYNC_CLKOP=64'b0100010001001001010100110100000101000010010011000100010101000100
    	FAST_LOCK=64'b0100010001001001010100110100000101000010010011000100010101000100
    	LOSS_LOCK_DETECTION=64'b0100010001001001010100110100000101000010010011000100010101000100
    	SCC_SS=64'b0100010001001001010100110100000101000010010011000100010101000100
    	SCC_FRACTIONAL=64'b0000000001000101010011100100000101000010010011000100010101000100
    	SATURATION=64'b0000000001000101010011100100000101000010010011000100010101000100
    	EN_PLLRESET=64'b0000000001000101010011100100000101000010010011000100010101000100
    	EN_CLKOP_OUT=24'b000000000100111101001110
    	EN_CLKOS_OUT=24'b010011110100011001000110
    	EN_CLKOS2_OUT=24'b010011110100011001000110
    	EN_CLKOS3_OUT=24'b010011110100011001000110
    	EN_CLKOS4_OUT=24'b010011110100011001000110
    	EN_CLKOS5_OUT=24'b010011110100011001000110
    	EN_CLKPHY_OUT=24'b010011110100011001000110
    	TEST_EN_CLK7_OUT=24'b010011110100011001000110
    	EN_CLKOP=24'b010110010100010101010011
    	EN_CLKOS=24'b000000000100111001001111
    	EN_CLKOS2=24'b000000000100111001001111
    	EN_CLKOS3=24'b000000000100111001001111
    	EN_CLKOS4=24'b000000000100111001001111
    	EN_CLKOS5=24'b000000000100111001001111
    	EN_CLKPHY=24'b000000000100111001001111
    	TEST_EN_CLK7=24'b000000000100111001001111
    	PHASE_SOURCE=48'b010100110101010001000001010101000100100101000011
    	CLKOP_FPHASE=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	CLKOS_FPHASE=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	CLKOS2_FPHASE=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	CLKOS3_FPHASE=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	CLKOS4_FPHASE=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	CLKOS5_FPHASE=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	CLKPHY_FPHASE=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	TEST_CLK7_FPHASE=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	CLKOP_CPHASE=80'b00000000000000000000000000000000000000000000000000000000001100010011011000110000
    	CLKOS_CPHASE=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	CLKOS2_CPHASE=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	CLKOS3_CPHASE=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	CLKOS4_CPHASE=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	CLKOS5_CPHASE=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	CLKOPHY_CPHASE=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	TEST_CLK7_CPHASE=80'b00000000000000000000000000000000000000000000000000000000000000000000000000110001
    	EN_PLL=56'b01000101010011100100000101000010010011000100010101000100
    	CONFIG_WAIT_FOR_LOCK=64'b0000000001000101010011100100000101000010010011000100010101000100
    	STATIC_PHASE_SEL=40'b0100001101001100010010110100111101010000
    	STATIC_PHASE_LOADREG=16'b0100111001001111
    	STATIC_VCO_PHASE_STEP=16'b0100111001001111
    	STATIC_VCO_PHASE_DIR=56'b01000100010001010100110001000001010110010100010101000100
       Generated name = pll_H_ipgen_lscc_pll_Z1_layer0
    @N:CG364 : lav-atx.v(9805) | Synthesizing module PLLC in library work.
    Running optimization stage 1 on PLLC .......
    Finished optimization stage 1 on PLLC (CPU Time 0h:00m:00s, Memory Used current: 125MB peak: 126MB)
    @W:CG360 : pll_H.v(314) | Removing wire clkout_testclk_o, as there is no assignment to it.
    @W:CG360 : pll_H.v(322) | Removing wire outresetack_testclk_o, as there is no assignment to it.
    @W:CG360 : pll_H.v(334) | Removing wire stepack_testclk_o, as there is no assignment to it.
    @W:CG360 : pll_H.v(357) | Removing wire apb_pready_o, as there is no assignment to it.
    @W:CG360 : pll_H.v(358) | Removing wire apb_pslverr_o, as there is no assignment to it.
    @W:CG360 : pll_H.v(359) | Removing wire apb_prdata_o, as there is no assignment to it.
    Running optimization stage 1 on pll_H_ipgen_lscc_pll_Z1_layer0 .......
    @W:CL318 : pll_H.v(314) | *Output clkout_testclk_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
    @W:CL318 : pll_H.v(322) | *Output outresetack_testclk_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
    @W:CL318 : pll_H.v(334) | *Output stepack_testclk_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
    @W:CL318 : pll_H.v(357) | *Output apb_pready_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
    @W:CL318 : pll_H.v(358) | *Output apb_pslverr_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
    @W:CL318 : pll_H.v(359) | *Output apb_prdata_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
    Finished optimization stage 1 on pll_H_ipgen_lscc_pll_Z1_layer0 (CPU Time 0h:00m:00s, Memory Used current: 125MB peak: 126MB)
    @N:CG364 : pll_H.v(11) | Synthesizing module pll_H in library work.
    Running optimization stage 1 on pll_H .......
    Finished optimization stage 1 on pll_H (CPU Time 0h:00m:00s, Memory Used current: 125MB peak: 126MB)
    @N:CG364 : blink_top.v(19) | Synthesizing module blink_top in library work.
    Running optimization stage 1 on blink_top .......
    @W:CL118 : blink_top.v(92) | Latch generated from always block for signal seg[6:0]; possible missing assignment in an if or case statement.
    @A:CL282 : blink_top.v(67) | Feedback mux created for signal wei[3:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
    Finished optimization stage 1 on blink_top (CPU Time 0h:00m:00s, Memory Used current: 126MB peak: 126MB)
    Running optimization stage 2 on blink_top .......
    Finished optimization stage 2 on blink_top (CPU Time 0h:00m:00s, Memory Used current: 126MB peak: 127MB)
    Running optimization stage 2 on pll_H .......
    Finished optimization stage 2 on pll_H (CPU Time 0h:00m:00s, Memory Used current: 126MB peak: 127MB)
    Running optimization stage 2 on PLLC .......
    Finished optimization stage 2 on PLLC (CPU Time 0h:00m:00s, Memory Used current: 126MB peak: 127MB)
    Running optimization stage 2 on pll_H_ipgen_lscc_pll_Z1_layer0 .......
    @N:CL159 : pll_H.v(298) | Input usr_fbkclk_i is unused.
    @N:CL159 : pll_H.v(306) | Input clken_testclk_i is unused.
    @N:CL159 : pll_H.v(350) | Input apb_pclk_i is unused.
    @N:CL159 : pll_H.v(351) | Input apb_preset_n_i is unused.
    @N:CL159 : pll_H.v(352) | Input apb_psel_i is unused.
    @N:CL159 : pll_H.v(353) | Input apb_penable_i is unused.
    @N:CL159 : pll_H.v(354) | Input apb_pwrite_i is unused.
    @N:CL159 : pll_H.v(355) | Input apb_paddr_i is unused.
    @N:CL159 : pll_H.v(356) | Input apb_pwdata_i is unused.
    Finished optimization stage 2 on pll_H_ipgen_lscc_pll_Z1_layer0 (CPU Time 0h:00m:00s, Memory Used current: 126MB peak: 127MB)

    For a summary of runtime per design unit, please see file:
    ==========================================================
    @L: D:\Avant_Versa_RevB\Avant-X Versa Board revB_Blink\impl_1\synwork\layer0.duruntime

    At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)

    Process completed successfully.
    # Mon Feb 19 09:55:58 2024

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-SP1
    Install: D:\radiant\2024.1\synpbase
    OS: Windows 10 or later
    Hostname: LSHITD0127

    Implementation : impl_1
    Synopsys Synopsys Netlist Linker, Version comp202303synp1, Build 218R, Built Oct 17 2023 09:25:20, @

    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 91MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Mon Feb 19 09:55:59 2024

    ###########################################################]

    For a summary of runtime and memory usage for all design units, please see file:
    ==========================================================
    @L: D:\Avant_Versa_RevB\Avant-X Versa Board revB_Blink\impl_1\synwork\Blink_RevB_impl_1_comp.rt.csv

    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 32MB)

    Process took 0h:00m:02s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Mon Feb 19 09:55:59 2024

    ###########################################################]

`
`

    ###########################################################[

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-SP1
    Install: D:\radiant\2024.1\synpbase
    OS: Windows 10 or later
    Hostname: LSHITD0127

    Implementation : impl_1
    Synopsys Synopsys Netlist Linker, Version comp202303synp1, Build 218R, Built Oct 17 2023 09:25:20, @

    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 91MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Mon Feb 19 09:56:00 2024

    ###########################################################]

`
`

    Premap Report

`
`

    # Mon Feb 19 09:56:01 2024

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-SP1
    Install: D:\radiant\2024.1\synpbase
    OS: Windows 10 or later
    Hostname: LSHITD0127

    Implementation : impl_1
    Synopsys Generic Technology Pre-mapping, Version map202303lat, Build 169R, Built Oct 17 2023 18:02:47, @

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 124MB)

    Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 138MB)

    Reading constraint file: D:\Avant_Versa_RevB\Avant-X Versa Board revB_Blink\impl_1\Blink_RevB_impl_1_cpe.ldc
    @L: D:\Avant_Versa_RevB\Avant-X Versa Board revB_Blink\impl_1\Blink_RevB_impl_1_scck.rpt
    See clock summary report "D:\Avant_Versa_RevB\Avant-X Versa Board revB_Blink\impl_1\Blink_RevB_impl_1_scck.rpt"
    @N:MF472 :  | Synthesis running in Automatic Compile Point mode
    @N:MF474 :  | No compile point is identified in Automatic Compile Point mode
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 138MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 138MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 138MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 138MB)

    NConnInternalConnection caching is on

    Starting HSTDM IP insertion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 185MB)

    Finished HSTDM IP insertion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 185MB)

    @N:MO111 : pll_h.v(359) | Tristate driver apb_prdata_o_1 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_1 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
    @N:MO111 : pll_h.v(359) | Tristate driver apb_prdata_o_2 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_2 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
    @N:MO111 : pll_h.v(359) | Tristate driver apb_prdata_o_3 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_3 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
    @N:MO111 : pll_h.v(359) | Tristate driver apb_prdata_o_4 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_4 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
    @N:MO111 : pll_h.v(359) | Tristate driver apb_prdata_o_5 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_5 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
    @N:MO111 : pll_h.v(359) | Tristate driver apb_prdata_o_6 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_6 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
    @N:MO111 : pll_h.v(359) | Tristate driver apb_prdata_o_7 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_7 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
    @N:MO111 : pll_h.v(359) | Tristate driver apb_prdata_o_8 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_8 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
    @N:MO111 : pll_h.v(359) | Tristate driver apb_prdata_o_9 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_9 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
    @N:MO111 : pll_h.v(359) | Tristate driver apb_prdata_o_10 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_10 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.

    Started DisTri Cleanup (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 185MB)

    Finished DisTri Cleanup (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 185MB)

    Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)

    Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)

    @N:FX1184 :  | Applying syn_allowed_resources blockrams=990 on top level netlist blink_top

    Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 187MB)

    Clock Summary
    ******************

              Start                                                            Requested     Requested     Clock        Clock                     Clock
    Level     Clock                                                            Frequency     Period        Type         Group                     Load
    ---------------------------------------------------------------------------------------------------------------------------------------------------
    0 -       pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock     200.0 MHz     5.000         inferred     Inferred_clkgroup_0_1     32

    0 -       blink_top|un1_seg21_inferred_clock                               200.0 MHz     5.000         inferred     Inferred_clkgroup_0_2     7
    ===================================================================================================================================================

    Clock Load Summary
    ***********************

                                                                     Clock     Source                                                                       Clock Pin       Non-clock Pin     Non-clock Pin
    Clock                                                            Load      Pin                                                                          Seq Example     Seq Example       Comb Example
    -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock     32        pll_inst.lscc_pll_inst.gen_ext_outclkdiv\.gen_no_clk7\.u_pll.CLKOP(PLLC)     wei[3:0].C      -                 -

    blink_top|un1_seg21_inferred_clock                               7         un1_seg21.OUT(or)                                                            seg[6:0].C      -                 -
    =======================================================================================================================================================================================================

    @W:MT530 : blink_top.v(67) | Found inferred clock pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock which controls 32 sequential elements including cnt[27:0]. This clock has no specified timing constraint which may adversely impact design performance.
    @W:MT530 : blink_top.v(92) | Found inferred clock blink_top|un1_seg21_inferred_clock which controls 7 sequential elements including seg[6:0]. This clock has no specified timing constraint which may adversely impact design performance.

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    1 non-gated/non-generated clock tree(s) driving 32 clock pin(s) of sequential element(s)
    1 gated/generated clock tree(s) driving 7 clock pin(s) of sequential element(s)
    0 instances converted, 7 sequential instances remain driven by gated/generated clocks

    ===================================================== Non-Gated/Non-Generated Clocks =====================================================
    Clock Tree ID     Driving Element                                                        Drive Element Type     Fanout     Sample Instance
    ------------------------------------------------------------------------------------------------------------------------------------------
    ClockId_0_0       pll_inst.lscc_pll_inst.gen_ext_outclkdiv\.gen_no_clk7\.u_pll.CLKOP     PLLC                   32         cnt[27:0]
    ==========================================================================================================================================
    ======================================================= Gated/Generated Clocks =======================================================
    Clock Tree ID     Driving Element     Drive Element Type     Unconverted Fanout     Sample Instance     Explanation
    --------------------------------------------------------------------------------------------------------------------------------------
    ClockId_0_1       un1_seg21.OUT       or                     7                      seg[6:0]            Clock Optimization not enabled
    ======================================================================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    @N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.

    Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB)

    Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 103MB peak: 189MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Mon Feb 19 09:56:03 2024

    ###########################################################]

`
`

    Map & Optimize Report

`
`

    # Mon Feb 19 09:56:03 2024

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-SP1
    Install: D:\radiant\2024.1\synpbase
    OS: Windows 10 or later
    Hostname: LSHITD0127

    Implementation : impl_1
    Synopsys Generic Technology Mapper, Version map202303lat, Build 169R, Built Oct 17 2023 18:02:47, @

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 124MB)

    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 138MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 126MB peak: 138MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 138MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 138MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)

    @N:MO111 : pll_h.v(359) | Tristate driver apb_prdata_o_1 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_1 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
    @N:MO111 : pll_h.v(359) | Tristate driver apb_prdata_o_2 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_2 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
    @N:MO111 : pll_h.v(359) | Tristate driver apb_prdata_o_3 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_3 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
    @N:MO111 : pll_h.v(359) | Tristate driver apb_prdata_o_4 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_4 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
    @N:MO111 : pll_h.v(359) | Tristate driver apb_prdata_o_5 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_5 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
    @N:MO111 : pll_h.v(359) | Tristate driver apb_prdata_o_6 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_6 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
    @N:MO111 : pll_h.v(359) | Tristate driver apb_prdata_o_7 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_7 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
    @N:MO111 : pll_h.v(359) | Tristate driver apb_prdata_o_8 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_8 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
    @N:MO111 : pll_h.v(359) | Tristate driver apb_prdata_o_9 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_9 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
    @N:MO111 : pll_h.v(359) | Tristate driver apb_prdata_o_10 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_10 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)

    Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 187MB peak: 187MB)

    Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 187MB peak: 187MB)

    Available hyper_sources - for debug and ip models
    	None Found

    NConnInternalConnection caching is on
    @W:BN132 : blink_top.v(67) | Removing sequential instance cnt_0[27:0] because it is equivalent to instance cnt[27:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 284MB peak: 295MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 284MB peak: 295MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 285MB peak: 295MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 285MB peak: 295MB)

    Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 285MB peak: 295MB)

    Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 285MB peak: 295MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:02s		    -0.01ns		  47 /        32
       2		0h:00m:02s		    -0.01ns		  47 /        32

       3		0h:00m:02s		    -0.01ns		  48 /        32
       4		0h:00m:02s		    -0.01ns		  48 /        32

       5		0h:00m:02s		    -0.01ns		  48 /        32

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 286MB peak: 295MB)

    @N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.

    Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 286MB peak: 295MB)

    Starting CDBProcessSetClockGroups... (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 286MB peak: 295MB)

    Finished with CDBProcessSetClockGroups (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 286MB peak: 295MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 239MB peak: 295MB)

    Writing Analyst data base D:\Avant_Versa_RevB\Avant-X Versa Board revB_Blink\impl_1\synwork\Blink_RevB_impl_1_m.srm
    Warning: Found 7 combinational loops!
    @W:BN137 :  | Found combinational loop during mapping at net lat_5
    1) instance I_40.lat (in view: work.blink_top(verilog)), output net lat_5 (in view: work.blink_top(verilog))
        net        lat_5
        input  pin I_40.lat/B
        instance   I_40.lat (cell LUT4)
        output pin I_40.lat/Z
        net        lat_5
    @W:BN137 :  | Found combinational loop during mapping at net lat_4
    2) instance I_39.lat (in view: work.blink_top(verilog)), output net lat_4 (in view: work.blink_top(verilog))
        net        lat_4
        input  pin I_39.lat/C
        instance   I_39.lat (cell LUT4)
        output pin I_39.lat/Z
        net        lat_4
    @W:BN137 :  | Found combinational loop during mapping at net lat_3
    3) instance I_38.lat (in view: work.blink_top(verilog)), output net lat_3 (in view: work.blink_top(verilog))
        net        lat_3
        input  pin I_38.lat/B
        instance   I_38.lat (cell LUT4)
        output pin I_38.lat/Z
        net        lat_3
    @W:BN137 :  | Found combinational loop during mapping at net lat_2
    4) instance I_37.lat (in view: work.blink_top(verilog)), output net lat_2 (in view: work.blink_top(verilog))
        net        lat_2
        input  pin I_37.lat/B
        instance   I_37.lat (cell LUT4)
        output pin I_37.lat/Z
        net        lat_2
    @W:BN137 :  | Found combinational loop during mapping at net lat_1
    5) instance I_43.lat (in view: work.blink_top(verilog)), output net lat_1 (in view: work.blink_top(verilog))
        net        lat_1
        input  pin I_43.lat/B
        instance   I_43.lat (cell LUT4)
        output pin I_43.lat/Z
        net        lat_1
    @W:BN137 :  | Found combinational loop during mapping at net lat_0
    6) instance I_42.lat (in view: work.blink_top(verilog)), output net lat_0 (in view: work.blink_top(verilog))
        net        lat_0
        input  pin I_42.lat/B
        instance   I_42.lat (cell LUT4)
        output pin I_42.lat/Z
        net        lat_0
    @W:BN137 :  | Found combinational loop during mapping at net lat
    7) instance I_41.lat (in view: work.blink_top(verilog)), output net lat (in view: work.blink_top(verilog))
        net        lat
        input  pin I_41.lat/B
        instance   I_41.lat (cell LUT4)
        output pin I_41.lat/Z
        net        lat
    End of loops

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 282MB peak: 295MB)

    Writing Verilog Simulation files

    Writing scf file... (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 283MB peak: 295MB)

    @N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 283MB peak: 295MB)

    Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 283MB peak: 295MB)

    Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 281MB peak: 295MB)

    Warning: Found 7 combinational loops!
    @W:BN137 :  | Found combinational loop during mapping at net lat_5
    1) instance I_40.lat (in view: work.blink_top(verilog)), output net lat_5 (in view: work.blink_top(verilog))
        net        lat_5
        input  pin I_40.lat/B
        instance   I_40.lat (cell LUT4)
        output pin I_40.lat/Z
        net        lat_5
    @W:BN137 :  | Found combinational loop during mapping at net lat_4
    2) instance I_39.lat (in view: work.blink_top(verilog)), output net lat_4 (in view: work.blink_top(verilog))
        net        lat_4
        input  pin I_39.lat/C
        instance   I_39.lat (cell LUT4)
        output pin I_39.lat/Z
        net        lat_4
    @W:BN137 :  | Found combinational loop during mapping at net lat_3
    3) instance I_38.lat (in view: work.blink_top(verilog)), output net lat_3 (in view: work.blink_top(verilog))
        net        lat_3
        input  pin I_38.lat/B
        instance   I_38.lat (cell LUT4)
        output pin I_38.lat/Z
        net        lat_3
    @W:BN137 :  | Found combinational loop during mapping at net lat_2
    4) instance I_37.lat (in view: work.blink_top(verilog)), output net lat_2 (in view: work.blink_top(verilog))
        net        lat_2
        input  pin I_37.lat/B
        instance   I_37.lat (cell LUT4)
        output pin I_37.lat/Z
        net        lat_2
    @W:BN137 :  | Found combinational loop during mapping at net lat_1
    5) instance I_43.lat (in view: work.blink_top(verilog)), output net lat_1 (in view: work.blink_top(verilog))
        net        lat_1
        input  pin I_43.lat/B
        instance   I_43.lat (cell LUT4)
        output pin I_43.lat/Z
        net        lat_1
    @W:BN137 :  | Found combinational loop during mapping at net lat_0
    6) instance I_42.lat (in view: work.blink_top(verilog)), output net lat_0 (in view: work.blink_top(verilog))
        net        lat_0
        input  pin I_42.lat/B
        instance   I_42.lat (cell LUT4)
        output pin I_42.lat/Z
        net        lat_0
    @W:BN137 :  | Found combinational loop during mapping at net lat
    7) instance I_41.lat (in view: work.blink_top(verilog)), output net lat (in view: work.blink_top(verilog))
        net        lat
        input  pin I_41.lat/B
        instance   I_41.lat (cell LUT4)
        output pin I_41.lat/Z
        net        lat
    End of loops
    @W:MT246 : pll_h.v(1480) | Blackbox PLLC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT420 :  | Found inferred clock pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll_inst.lscc_pll_inst.clk_25[0].
    @W:MT420 :  | Found inferred clock blink_top|un1_seg21_inferred_clock with period 5.00ns. Please declare a user-defined clock on net I_37.lat_e.

    ##### START OF TIMING REPORT #####[
    # Timing report written on Mon Feb 19 09:56:07 2024
    #

    Top view:               blink_top
    Requested Frequency:    200.0 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):    D:\Avant_Versa_RevB\Avant-X Versa Board revB_Blink\impl_1\Blink_RevB_impl_1_cpe.ldc

    @N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: -0.434

    @N:MT286 :  | System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
                                                                     Requested     Estimated     Requested     Estimated                Clock        Clock
    Starting Clock                                                   Frequency     Frequency     Period        Period        Slack      Type         Group
    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------
    blink_top|un1_seg21_inferred_clock                               200.0 MHz     NA            5.000         NA            NA         inferred     Inferred_clkgroup_0_2
    pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock     200.0 MHz     184.0 MHz     5.000         5.434         -0.434     inferred     Inferred_clkgroup_0_1
    System                                                           200.0 MHz     NA            5.000         0.000         5.000      system       system_clkgroup
    ======================================================================================================================================================================
    Estimated period and frequency reported as NA means no slack depends directly on the clock waveform

    Clock Relationships
    *******************

    Clocks                                                                                                                      |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                                                      Ending                                                        |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    System                                                        System                                                        |  5.000       5.000   |  No paths    -      |  No paths    -      |  No paths    -
    pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock  pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock  |  5.000       -0.434  |  No paths    -      |  No paths    -      |  No paths    -
    ===================================================================================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                 Starting                                                                                                 Arrival
    Instance     Reference                                                        Type        Pin     Net                 Time        Slack
                 Clock
    ----------------------------------------------------------------------------------------------------------------------------------------
    cnt[0]       pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock     FD1P3DX     Q       cnt[0]              0.907       -0.434
    cnt[1]       pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock     FD1P3DX     Q       cnt[1]              0.907       -0.434
    cnt[2]       pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock     FD1P3DX     Q       cnt[2]              0.907       -0.434
    cnt[3]       pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock     FD1P3DX     Q       cnt[3]              0.907       -0.434
    cnt[4]       pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock     FD1P3DX     Q       cnt[4]              0.907       -0.434
    cnt[5]       pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock     FD1P3DX     Q       cnt[5]              0.907       -0.434
    cnt[6]       pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock     FD1P3DX     Q       un1_cnt_1_axb_6     0.907       -0.434
    cnt[7]       pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock     FD1P3DX     Q       cnt[7]              0.907       -0.434
    cnt[8]       pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock     FD1P3DX     Q       cnt[8]              0.907       -0.434
    cnt[9]       pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock     FD1P3DX     Q       cnt[9]              0.907       -0.434
    ========================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                 Starting                                                                                                   Required
    Instance     Reference                                                        Type        Pin     Net                   Time         Slack
                 Clock
    -------------------------------------------------------------------------------------------------------------------------------------------
    cnt[24]      pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock     FD1P3DX     D       dsp_join_kb_0[24]     4.946        -0.434
    cnt[22]      pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock     FD1P3DX     D       dsp_join_kb_0[22]     4.946        -0.373
    cnt[20]      pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock     FD1P3DX     D       dsp_join_kb_0[20]     4.946        -0.312
    cnt[21]      pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock     FD1P3DX     D       dsp_join_kb_0[21]     4.946        -0.312
    cnt[18]      pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock     FD1P3DX     D       dsp_join_kb_0[18]     4.946        -0.252
    cnt[19]      pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock     FD1P3DX     D       dsp_join_kb_0[19]     4.946        -0.252
    cnt[16]      pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock     FD1P3DX     D       dsp_join_kb_0[16]     4.946        -0.191
    cnt[14]      pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock     FD1P3DX     D       dsp_join_kb_0[14]     4.946        -0.130
    cnt[12]      pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock     FD1P3DX     D       dsp_join_kb_0[12]     4.946        -0.069
    cnt[13]      pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock     FD1P3DX     D       dsp_join_kb_0[13]     4.946        -0.069
    ===========================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      5.000
        - Setup time:                            0.054
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.946

        - Propagation time:                      5.380
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.434

        Number of logic level(s):                17
        Starting point:                          cnt[0] / Q
        Ending point:                            cnt[24] / D
        The start point is clocked by            pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
        The end   point is clocked by            pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK

    Instance / Net                        Pin      Pin               Arrival     No. of
    Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------
    cnt[0]                    FD1P3DX     Q        Out     0.907     0.907 r     -
    cnt[0]                    Net         -        -       -         -           2
    cnt8_19                   LUT4        A        In      0.000     0.907 r     -
    cnt8_19                   LUT4        Z        Out     0.390     1.297 f     -
    cnt8_19                   Net         -        -       -         -           1
    cnt8_25                   LUT4        D        In      0.000     1.297 f     -
    cnt8_25                   LUT4        Z        Out     0.819     2.116 f     -
    cnt8_25                   Net         -        -       -         -           14
    un1_cnt_1_cry_0_0_RNO     LUT4        D        In      0.000     2.116 f     -
    un1_cnt_1_cry_0_0_RNO     LUT4        Z        Out     0.606     2.722 f     -
    cnt9_i                    Net         -        -       -         -           1
    un1_cnt_1_cry_0_0         CCU2C       C0       In      0.000     2.722 f     -
    un1_cnt_1_cry_0_0         CCU2C       COUT     Out     0.900     3.622 r     -
    un1_cnt_1_cry_1           Net         -        -       -         -           1
    un1_cnt_1_cry_2_0         CCU2C       CIN      In      0.000     3.622 r     -
    un1_cnt_1_cry_2_0         CCU2C       COUT     Out     0.061     3.683 r     -
    un1_cnt_1_cry_3           Net         -        -       -         -           1
    un1_cnt_1_cry_4_0         CCU2C       CIN      In      0.000     3.683 r     -
    un1_cnt_1_cry_4_0         CCU2C       COUT     Out     0.061     3.744 r     -
    un1_cnt_1_cry_5           Net         -        -       -         -           1
    un1_cnt_1_cry_6_0         CCU2C       CIN      In      0.000     3.744 r     -
    un1_cnt_1_cry_6_0         CCU2C       COUT     Out     0.061     3.805 r     -
    un1_cnt_1_cry_7           Net         -        -       -         -           1
    un1_cnt_1_cry_8_0         CCU2C       CIN      In      0.000     3.805 r     -
    un1_cnt_1_cry_8_0         CCU2C       COUT     Out     0.061     3.866 r     -
    un1_cnt_1_cry_9           Net         -        -       -         -           1
    un1_cnt_1_cry_10_0        CCU2C       CIN      In      0.000     3.866 r     -
    un1_cnt_1_cry_10_0        CCU2C       COUT     Out     0.061     3.927 r     -
    un1_cnt_1_cry_11          Net         -        -       -         -           1
    un1_cnt_1_cry_12_0        CCU2C       CIN      In      0.000     3.927 r     -
    un1_cnt_1_cry_12_0        CCU2C       COUT     Out     0.061     3.988 r     -
    un1_cnt_1_cry_13          Net         -        -       -         -           1
    un1_cnt_1_cry_14_0        CCU2C       CIN      In      0.000     3.988 r     -
    un1_cnt_1_cry_14_0        CCU2C       COUT     Out     0.061     4.049 r     -
    un1_cnt_1_cry_15          Net         -        -       -         -           1
    un1_cnt_1_cry_16_0        CCU2C       CIN      In      0.000     4.049 r     -
    un1_cnt_1_cry_16_0        CCU2C       COUT     Out     0.061     4.110 r     -
    un1_cnt_1_cry_17          Net         -        -       -         -           1
    un1_cnt_1_cry_18_0        CCU2C       CIN      In      0.000     4.110 r     -
    un1_cnt_1_cry_18_0        CCU2C       COUT     Out     0.061     4.171 r     -
    un1_cnt_1_cry_19          Net         -        -       -         -           1
    un1_cnt_1_cry_20_0        CCU2C       CIN      In      0.000     4.171 r     -
    un1_cnt_1_cry_20_0        CCU2C       COUT     Out     0.061     4.232 r     -
    un1_cnt_1_cry_21          Net         -        -       -         -           1
    un1_cnt_1_cry_22_0        CCU2C       CIN      In      0.000     4.232 r     -
    un1_cnt_1_cry_22_0        CCU2C       COUT     Out     0.061     4.293 r     -
    un1_cnt_1_cry_23          Net         -        -       -         -           1
    un1_cnt_1_cry_24_0        CCU2C       CIN      In      0.000     4.293 r     -
    un1_cnt_1_cry_24_0        CCU2C       S0       Out     0.481     4.774 r     -
    un1_cnt_1_cry_24_0_S0     Net         -        -       -         -           1
    cnt_3[24]                 LUT4        A        In      0.000     4.774 r     -
    cnt_3[24]                 LUT4        Z        Out     0.606     5.380 r     -
    dsp_join_kb_0[24]         Net         -        -       -         -           1
    cnt[24]                   FD1P3DX     D        In      0.000     5.380 r     -
    =======================================================================================

    Path information for path number 2:
          Requested Period:                      5.000
        - Setup time:                            0.054
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.946

        - Propagation time:                      5.380
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.434

        Number of logic level(s):                17
        Starting point:                          cnt[1] / Q
        Ending point:                            cnt[24] / D
        The start point is clocked by            pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
        The end   point is clocked by            pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK

    Instance / Net                        Pin      Pin               Arrival     No. of
    Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------
    cnt[1]                    FD1P3DX     Q        Out     0.907     0.907 r     -
    cnt[1]                    Net         -        -       -         -           2
    cnt8_19                   LUT4        B        In      0.000     0.907 r     -
    cnt8_19                   LUT4        Z        Out     0.390     1.297 f     -
    cnt8_19                   Net         -        -       -         -           1
    cnt8_25                   LUT4        D        In      0.000     1.297 f     -
    cnt8_25                   LUT4        Z        Out     0.819     2.116 f     -
    cnt8_25                   Net         -        -       -         -           14
    un1_cnt_1_cry_0_0_RNO     LUT4        D        In      0.000     2.116 f     -
    un1_cnt_1_cry_0_0_RNO     LUT4        Z        Out     0.606     2.722 f     -
    cnt9_i                    Net         -        -       -         -           1
    un1_cnt_1_cry_0_0         CCU2C       C0       In      0.000     2.722 f     -
    un1_cnt_1_cry_0_0         CCU2C       COUT     Out     0.900     3.622 r     -
    un1_cnt_1_cry_1           Net         -        -       -         -           1
    un1_cnt_1_cry_2_0         CCU2C       CIN      In      0.000     3.622 r     -
    un1_cnt_1_cry_2_0         CCU2C       COUT     Out     0.061     3.683 r     -
    un1_cnt_1_cry_3           Net         -        -       -         -           1
    un1_cnt_1_cry_4_0         CCU2C       CIN      In      0.000     3.683 r     -
    un1_cnt_1_cry_4_0         CCU2C       COUT     Out     0.061     3.744 r     -
    un1_cnt_1_cry_5           Net         -        -       -         -           1
    un1_cnt_1_cry_6_0         CCU2C       CIN      In      0.000     3.744 r     -
    un1_cnt_1_cry_6_0         CCU2C       COUT     Out     0.061     3.805 r     -
    un1_cnt_1_cry_7           Net         -        -       -         -           1
    un1_cnt_1_cry_8_0         CCU2C       CIN      In      0.000     3.805 r     -
    un1_cnt_1_cry_8_0         CCU2C       COUT     Out     0.061     3.866 r     -
    un1_cnt_1_cry_9           Net         -        -       -         -           1
    un1_cnt_1_cry_10_0        CCU2C       CIN      In      0.000     3.866 r     -
    un1_cnt_1_cry_10_0        CCU2C       COUT     Out     0.061     3.927 r     -
    un1_cnt_1_cry_11          Net         -        -       -         -           1
    un1_cnt_1_cry_12_0        CCU2C       CIN      In      0.000     3.927 r     -
    un1_cnt_1_cry_12_0        CCU2C       COUT     Out     0.061     3.988 r     -
    un1_cnt_1_cry_13          Net         -        -       -         -           1
    un1_cnt_1_cry_14_0        CCU2C       CIN      In      0.000     3.988 r     -
    un1_cnt_1_cry_14_0        CCU2C       COUT     Out     0.061     4.049 r     -
    un1_cnt_1_cry_15          Net         -        -       -         -           1
    un1_cnt_1_cry_16_0        CCU2C       CIN      In      0.000     4.049 r     -
    un1_cnt_1_cry_16_0        CCU2C       COUT     Out     0.061     4.110 r     -
    un1_cnt_1_cry_17          Net         -        -       -         -           1
    un1_cnt_1_cry_18_0        CCU2C       CIN      In      0.000     4.110 r     -
    un1_cnt_1_cry_18_0        CCU2C       COUT     Out     0.061     4.171 r     -
    un1_cnt_1_cry_19          Net         -        -       -         -           1
    un1_cnt_1_cry_20_0        CCU2C       CIN      In      0.000     4.171 r     -
    un1_cnt_1_cry_20_0        CCU2C       COUT     Out     0.061     4.232 r     -
    un1_cnt_1_cry_21          Net         -        -       -         -           1
    un1_cnt_1_cry_22_0        CCU2C       CIN      In      0.000     4.232 r     -
    un1_cnt_1_cry_22_0        CCU2C       COUT     Out     0.061     4.293 r     -
    un1_cnt_1_cry_23          Net         -        -       -         -           1
    un1_cnt_1_cry_24_0        CCU2C       CIN      In      0.000     4.293 r     -
    un1_cnt_1_cry_24_0        CCU2C       S0       Out     0.481     4.774 r     -
    un1_cnt_1_cry_24_0_S0     Net         -        -       -         -           1
    cnt_3[24]                 LUT4        A        In      0.000     4.774 r     -
    cnt_3[24]                 LUT4        Z        Out     0.606     5.380 r     -
    dsp_join_kb_0[24]         Net         -        -       -         -           1
    cnt[24]                   FD1P3DX     D        In      0.000     5.380 r     -
    =======================================================================================

    Path information for path number 3:
          Requested Period:                      5.000
        - Setup time:                            0.054
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.946

        - Propagation time:                      5.380
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.434

        Number of logic level(s):                17
        Starting point:                          cnt[2] / Q
        Ending point:                            cnt[24] / D
        The start point is clocked by            pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
        The end   point is clocked by            pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK

    Instance / Net                        Pin      Pin               Arrival     No. of
    Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------
    cnt[2]                    FD1P3DX     Q        Out     0.907     0.907 r     -
    cnt[2]                    Net         -        -       -         -           2
    cnt8_19                   LUT4        C        In      0.000     0.907 r     -
    cnt8_19                   LUT4        Z        Out     0.390     1.297 f     -
    cnt8_19                   Net         -        -       -         -           1
    cnt8_25                   LUT4        D        In      0.000     1.297 f     -
    cnt8_25                   LUT4        Z        Out     0.819     2.116 f     -
    cnt8_25                   Net         -        -       -         -           14
    un1_cnt_1_cry_0_0_RNO     LUT4        D        In      0.000     2.116 f     -
    un1_cnt_1_cry_0_0_RNO     LUT4        Z        Out     0.606     2.722 f     -
    cnt9_i                    Net         -        -       -         -           1
    un1_cnt_1_cry_0_0         CCU2C       C0       In      0.000     2.722 f     -
    un1_cnt_1_cry_0_0         CCU2C       COUT     Out     0.900     3.622 r     -
    un1_cnt_1_cry_1           Net         -        -       -         -           1
    un1_cnt_1_cry_2_0         CCU2C       CIN      In      0.000     3.622 r     -
    un1_cnt_1_cry_2_0         CCU2C       COUT     Out     0.061     3.683 r     -
    un1_cnt_1_cry_3           Net         -        -       -         -           1
    un1_cnt_1_cry_4_0         CCU2C       CIN      In      0.000     3.683 r     -
    un1_cnt_1_cry_4_0         CCU2C       COUT     Out     0.061     3.744 r     -
    un1_cnt_1_cry_5           Net         -        -       -         -           1
    un1_cnt_1_cry_6_0         CCU2C       CIN      In      0.000     3.744 r     -
    un1_cnt_1_cry_6_0         CCU2C       COUT     Out     0.061     3.805 r     -
    un1_cnt_1_cry_7           Net         -        -       -         -           1
    un1_cnt_1_cry_8_0         CCU2C       CIN      In      0.000     3.805 r     -
    un1_cnt_1_cry_8_0         CCU2C       COUT     Out     0.061     3.866 r     -
    un1_cnt_1_cry_9           Net         -        -       -         -           1
    un1_cnt_1_cry_10_0        CCU2C       CIN      In      0.000     3.866 r     -
    un1_cnt_1_cry_10_0        CCU2C       COUT     Out     0.061     3.927 r     -
    un1_cnt_1_cry_11          Net         -        -       -         -           1
    un1_cnt_1_cry_12_0        CCU2C       CIN      In      0.000     3.927 r     -
    un1_cnt_1_cry_12_0        CCU2C       COUT     Out     0.061     3.988 r     -
    un1_cnt_1_cry_13          Net         -        -       -         -           1
    un1_cnt_1_cry_14_0        CCU2C       CIN      In      0.000     3.988 r     -
    un1_cnt_1_cry_14_0        CCU2C       COUT     Out     0.061     4.049 r     -
    un1_cnt_1_cry_15          Net         -        -       -         -           1
    un1_cnt_1_cry_16_0        CCU2C       CIN      In      0.000     4.049 r     -
    un1_cnt_1_cry_16_0        CCU2C       COUT     Out     0.061     4.110 r     -
    un1_cnt_1_cry_17          Net         -        -       -         -           1
    un1_cnt_1_cry_18_0        CCU2C       CIN      In      0.000     4.110 r     -
    un1_cnt_1_cry_18_0        CCU2C       COUT     Out     0.061     4.171 r     -
    un1_cnt_1_cry_19          Net         -        -       -         -           1
    un1_cnt_1_cry_20_0        CCU2C       CIN      In      0.000     4.171 r     -
    un1_cnt_1_cry_20_0        CCU2C       COUT     Out     0.061     4.232 r     -
    un1_cnt_1_cry_21          Net         -        -       -         -           1
    un1_cnt_1_cry_22_0        CCU2C       CIN      In      0.000     4.232 r     -
    un1_cnt_1_cry_22_0        CCU2C       COUT     Out     0.061     4.293 r     -
    un1_cnt_1_cry_23          Net         -        -       -         -           1
    un1_cnt_1_cry_24_0        CCU2C       CIN      In      0.000     4.293 r     -
    un1_cnt_1_cry_24_0        CCU2C       S0       Out     0.481     4.774 r     -
    un1_cnt_1_cry_24_0_S0     Net         -        -       -         -           1
    cnt_3[24]                 LUT4        A        In      0.000     4.774 r     -
    cnt_3[24]                 LUT4        Z        Out     0.606     5.380 r     -
    dsp_join_kb_0[24]         Net         -        -       -         -           1
    cnt[24]                   FD1P3DX     D        In      0.000     5.380 r     -
    =======================================================================================

    Path information for path number 4:
          Requested Period:                      5.000
        - Setup time:                            0.054
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.946

        - Propagation time:                      5.380
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.434

        Number of logic level(s):                17
        Starting point:                          cnt[3] / Q
        Ending point:                            cnt[24] / D
        The start point is clocked by            pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
        The end   point is clocked by            pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK

    Instance / Net                        Pin      Pin               Arrival     No. of
    Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------
    cnt[3]                    FD1P3DX     Q        Out     0.907     0.907 r     -
    cnt[3]                    Net         -        -       -         -           2
    cnt8_19                   LUT4        D        In      0.000     0.907 r     -
    cnt8_19                   LUT4        Z        Out     0.390     1.297 f     -
    cnt8_19                   Net         -        -       -         -           1
    cnt8_25                   LUT4        D        In      0.000     1.297 f     -
    cnt8_25                   LUT4        Z        Out     0.819     2.116 f     -
    cnt8_25                   Net         -        -       -         -           14
    un1_cnt_1_cry_0_0_RNO     LUT4        D        In      0.000     2.116 f     -
    un1_cnt_1_cry_0_0_RNO     LUT4        Z        Out     0.606     2.722 f     -
    cnt9_i                    Net         -        -       -         -           1
    un1_cnt_1_cry_0_0         CCU2C       C0       In      0.000     2.722 f     -
    un1_cnt_1_cry_0_0         CCU2C       COUT     Out     0.900     3.622 r     -
    un1_cnt_1_cry_1           Net         -        -       -         -           1
    un1_cnt_1_cry_2_0         CCU2C       CIN      In      0.000     3.622 r     -
    un1_cnt_1_cry_2_0         CCU2C       COUT     Out     0.061     3.683 r     -
    un1_cnt_1_cry_3           Net         -        -       -         -           1
    un1_cnt_1_cry_4_0         CCU2C       CIN      In      0.000     3.683 r     -
    un1_cnt_1_cry_4_0         CCU2C       COUT     Out     0.061     3.744 r     -
    un1_cnt_1_cry_5           Net         -        -       -         -           1
    un1_cnt_1_cry_6_0         CCU2C       CIN      In      0.000     3.744 r     -
    un1_cnt_1_cry_6_0         CCU2C       COUT     Out     0.061     3.805 r     -
    un1_cnt_1_cry_7           Net         -        -       -         -           1
    un1_cnt_1_cry_8_0         CCU2C       CIN      In      0.000     3.805 r     -
    un1_cnt_1_cry_8_0         CCU2C       COUT     Out     0.061     3.866 r     -
    un1_cnt_1_cry_9           Net         -        -       -         -           1
    un1_cnt_1_cry_10_0        CCU2C       CIN      In      0.000     3.866 r     -
    un1_cnt_1_cry_10_0        CCU2C       COUT     Out     0.061     3.927 r     -
    un1_cnt_1_cry_11          Net         -        -       -         -           1
    un1_cnt_1_cry_12_0        CCU2C       CIN      In      0.000     3.927 r     -
    un1_cnt_1_cry_12_0        CCU2C       COUT     Out     0.061     3.988 r     -
    un1_cnt_1_cry_13          Net         -        -       -         -           1
    un1_cnt_1_cry_14_0        CCU2C       CIN      In      0.000     3.988 r     -
    un1_cnt_1_cry_14_0        CCU2C       COUT     Out     0.061     4.049 r     -
    un1_cnt_1_cry_15          Net         -        -       -         -           1
    un1_cnt_1_cry_16_0        CCU2C       CIN      In      0.000     4.049 r     -
    un1_cnt_1_cry_16_0        CCU2C       COUT     Out     0.061     4.110 r     -
    un1_cnt_1_cry_17          Net         -        -       -         -           1
    un1_cnt_1_cry_18_0        CCU2C       CIN      In      0.000     4.110 r     -
    un1_cnt_1_cry_18_0        CCU2C       COUT     Out     0.061     4.171 r     -
    un1_cnt_1_cry_19          Net         -        -       -         -           1
    un1_cnt_1_cry_20_0        CCU2C       CIN      In      0.000     4.171 r     -
    un1_cnt_1_cry_20_0        CCU2C       COUT     Out     0.061     4.232 r     -
    un1_cnt_1_cry_21          Net         -        -       -         -           1
    un1_cnt_1_cry_22_0        CCU2C       CIN      In      0.000     4.232 r     -
    un1_cnt_1_cry_22_0        CCU2C       COUT     Out     0.061     4.293 r     -
    un1_cnt_1_cry_23          Net         -        -       -         -           1
    un1_cnt_1_cry_24_0        CCU2C       CIN      In      0.000     4.293 r     -
    un1_cnt_1_cry_24_0        CCU2C       S0       Out     0.481     4.774 r     -
    un1_cnt_1_cry_24_0_S0     Net         -        -       -         -           1
    cnt_3[24]                 LUT4        A        In      0.000     4.774 r     -
    cnt_3[24]                 LUT4        Z        Out     0.606     5.380 r     -
    dsp_join_kb_0[24]         Net         -        -       -         -           1
    cnt[24]                   FD1P3DX     D        In      0.000     5.380 r     -
    =======================================================================================

    Path information for path number 5:
          Requested Period:                      5.000
        - Setup time:                            0.054
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.946

        - Propagation time:                      5.380
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.434

        Number of logic level(s):                17
        Starting point:                          cnt[4] / Q
        Ending point:                            cnt[24] / D
        The start point is clocked by            pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
        The end   point is clocked by            pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK

    Instance / Net                        Pin      Pin               Arrival     No. of
    Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------
    cnt[4]                    FD1P3DX     Q        Out     0.907     0.907 r     -
    cnt[4]                    Net         -        -       -         -           2
    cnt8_17                   LUT4        A        In      0.000     0.907 r     -
    cnt8_17                   LUT4        Z        Out     0.390     1.297 f     -
    cnt8_17                   Net         -        -       -         -           1
    cnt8_25                   LUT4        B        In      0.000     1.297 f     -
    cnt8_25                   LUT4        Z        Out     0.819     2.116 f     -
    cnt8_25                   Net         -        -       -         -           14
    un1_cnt_1_cry_0_0_RNO     LUT4        D        In      0.000     2.116 f     -
    un1_cnt_1_cry_0_0_RNO     LUT4        Z        Out     0.606     2.722 f     -
    cnt9_i                    Net         -        -       -         -           1
    un1_cnt_1_cry_0_0         CCU2C       C0       In      0.000     2.722 f     -
    un1_cnt_1_cry_0_0         CCU2C       COUT     Out     0.900     3.622 r     -
    un1_cnt_1_cry_1           Net         -        -       -         -           1
    un1_cnt_1_cry_2_0         CCU2C       CIN      In      0.000     3.622 r     -
    un1_cnt_1_cry_2_0         CCU2C       COUT     Out     0.061     3.683 r     -
    un1_cnt_1_cry_3           Net         -        -       -         -           1
    un1_cnt_1_cry_4_0         CCU2C       CIN      In      0.000     3.683 r     -
    un1_cnt_1_cry_4_0         CCU2C       COUT     Out     0.061     3.744 r     -
    un1_cnt_1_cry_5           Net         -        -       -         -           1
    un1_cnt_1_cry_6_0         CCU2C       CIN      In      0.000     3.744 r     -
    un1_cnt_1_cry_6_0         CCU2C       COUT     Out     0.061     3.805 r     -
    un1_cnt_1_cry_7           Net         -        -       -         -           1
    un1_cnt_1_cry_8_0         CCU2C       CIN      In      0.000     3.805 r     -
    un1_cnt_1_cry_8_0         CCU2C       COUT     Out     0.061     3.866 r     -
    un1_cnt_1_cry_9           Net         -        -       -         -           1
    un1_cnt_1_cry_10_0        CCU2C       CIN      In      0.000     3.866 r     -
    un1_cnt_1_cry_10_0        CCU2C       COUT     Out     0.061     3.927 r     -
    un1_cnt_1_cry_11          Net         -        -       -         -           1
    un1_cnt_1_cry_12_0        CCU2C       CIN      In      0.000     3.927 r     -
    un1_cnt_1_cry_12_0        CCU2C       COUT     Out     0.061     3.988 r     -
    un1_cnt_1_cry_13          Net         -        -       -         -           1
    un1_cnt_1_cry_14_0        CCU2C       CIN      In      0.000     3.988 r     -
    un1_cnt_1_cry_14_0        CCU2C       COUT     Out     0.061     4.049 r     -
    un1_cnt_1_cry_15          Net         -        -       -         -           1
    un1_cnt_1_cry_16_0        CCU2C       CIN      In      0.000     4.049 r     -
    un1_cnt_1_cry_16_0        CCU2C       COUT     Out     0.061     4.110 r     -
    un1_cnt_1_cry_17          Net         -        -       -         -           1
    un1_cnt_1_cry_18_0        CCU2C       CIN      In      0.000     4.110 r     -
    un1_cnt_1_cry_18_0        CCU2C       COUT     Out     0.061     4.171 r     -
    un1_cnt_1_cry_19          Net         -        -       -         -           1
    un1_cnt_1_cry_20_0        CCU2C       CIN      In      0.000     4.171 r     -
    un1_cnt_1_cry_20_0        CCU2C       COUT     Out     0.061     4.232 r     -
    un1_cnt_1_cry_21          Net         -        -       -         -           1
    un1_cnt_1_cry_22_0        CCU2C       CIN      In      0.000     4.232 r     -
    un1_cnt_1_cry_22_0        CCU2C       COUT     Out     0.061     4.293 r     -
    un1_cnt_1_cry_23          Net         -        -       -         -           1
    un1_cnt_1_cry_24_0        CCU2C       CIN      In      0.000     4.293 r     -
    un1_cnt_1_cry_24_0        CCU2C       S0       Out     0.481     4.774 r     -
    un1_cnt_1_cry_24_0_S0     Net         -        -       -         -           1
    cnt_3[24]                 LUT4        A        In      0.000     4.774 r     -
    cnt_3[24]                 LUT4        Z        Out     0.606     5.380 r     -
    dsp_join_kb_0[24]         Net         -        -       -         -           1
    cnt[24]                   FD1P3DX     D        In      0.000     5.380 r     -
    =======================================================================================

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                          Starting                                    Arrival
    Instance              Reference     Type     Pin     Net          Time        Slack
                          Clock
    -----------------------------------------------------------------------------------
    sw12_ibuf_RNII395     System        INV      Z       sw12_c_i     0.000       5.000
    ===================================================================================

    Ending Points with Worst Slack
    ******************************

                                                                     Starting                                      Required
    Instance                                                         Reference     Type     Pin       Net          Time         Slack
                                                                     Clock
    ---------------------------------------------------------------------------------------------------------------------------------
    pll_inst.lscc_pll_inst.gen_ext_outclkdiv\.gen_no_clk7\.u_pll     System        PLLC     RESET     sw12_c_i     5.000        5.000
    =================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      5.000
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         5.000

        - Propagation time:                      0.000
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 5.000

        Number of logic level(s):                0
        Starting point:                          sw12_ibuf_RNII395 / Z
        Ending point:                            pll_inst.lscc_pll_inst.gen_ext_outclkdiv\.gen_no_clk7\.u_pll / RESET
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                                                            Pin       Pin               Arrival     No. of
    Name                                                             Type     Name      Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------------------------
    sw12_ibuf_RNII395                                                INV      Z         Out     0.000     0.000 r     -
    sw12_c_i                                                         Net      -         -       -         -           29
    pll_inst.lscc_pll_inst.gen_ext_outclkdiv\.gen_no_clk7\.u_pll     PLLC     RESET     In      0.000     0.000 r     -
    ============================================================================================================================

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied

    Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 282MB peak: 295MB)

    Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 282MB peak: 295MB)

    ---------------------------------------
    Resource Usage Report
    Part: lav_at_x70lfg1156c-3

    Register bits: 32 of 397440 (0%)
    I/O cells:       16

    Details:
    CCU2C:          14
    FD1P3DX:        28
    FD1P3IX:        4
    GSRA:           1
    IB:             5
    INV:            1
    LUT4:           47
    OB:             11
    PLLC:           1
    VHI:            3
    VLO:            3

    Resource Usage inside macros:
    Registers: 0
    LUTs: 0
    EBRs: 0
    DSPs: 0
    Distributed RAMs: 0
    Carry Chains: 0
    Blackboxes: 0

    Mapping Summary:
    Total number of registers: 32 + 0 = 32 of 397440 (0.01%)
    Total number of LUTs: 47 + 0 = 47
    Total number of EBRs: 0 + 0 = 0 of 990 (0.00%)
    Total number of DSPs: 0 + 0 = 0 of 1800 (0.00%)
    Total number of Distributed RAMs: 0 + 0 = 0
    Total number of Carry Chains: 14 + 0 = 14
    Total number of BlackBoxes: 8 + 0 = 8
    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 295MB)

    Process took 0h:00m:03s realtime, 0h:00m:03s cputime
    # Mon Feb 19 09:56:07 2024

    ###########################################################]

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