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    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-SP1
    Install: D:\radiant\2024.1\synpbase
    OS: Windows 10 or later
    Hostname: LSHITD0127

    Implementation : impl_1

    # Written on Mon Feb 19 09:56:03 2024

    ##### DESIGN INFO #######################################################

    Top View:                "blink_top"
    Constraint File(s):      "D:\Avant_Versa_RevB\Avant-X Versa Board revB_Blink\impl_1\Blink_RevB_impl_1_cpe.ldc"

    ##### SUMMARY ############################################################

    Found 0 issues in 0 out of 1 constraints

    ##### DETAILS ############################################################

    Clock Relationships
    *******************

    Starting                                                         Ending                                                           |     rise to rise     |     fall to fall     |     rise to fall     |     fall to rise
    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock     pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock     |     5.000            |     No paths         |     No paths         |     No paths
    pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock     blink_top|un1_seg21_inferred_clock                               |     No paths         |     No paths         |     Diff grp         |     No paths
    =============================================================================================================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Unconstrained Start/End Points
    ******************************

    p:clk_in
    p:seg1
    p:seg2
    p:seg3
    p:seg_a
    p:seg_b
    p:seg_c
    p:seg_d
    p:seg_dp
    p:seg_e
    p:seg_f
    p:seg_g
    p:sw12
    p:sw13
    p:sw14
    p:sw15

    Inapplicable constraints
    ************************

    (none)

    Applicable constraints with issues
    **********************************

    (none)

    Constraints with matching wildcard expressions
    **********************************************

    (none)

    Library Report
    **************

    # End of Constraint Checker Report

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