@W: MT530 :"d:\avant_versa_revb\avant-x versa board revb_blink\source\impl_1\blink_top.v":67:0:67:5|Found inferred clock pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock which controls 32 sequential elements including cnt[27:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\avant_versa_revb\avant-x versa board revb_blink\source\impl_1\blink_top.v":92:1:92:4|Found inferred clock blink_top|un1_seg21_inferred_clock which controls 7 sequential elements including seg[6:0]. This clock has no specified timing constraint which may adversely impact design performance. 
