    POSTSYN: Post Synthesis Process Radiant Software (64-bit) 2024.1.t.30.0
    Command Line: postsyn -a LAV-AT -p LAV-AT-X70 -t LFG1156 -sp 3 -oc Commercial -top -w -o Blink_RevB_impl_1_syn.udb -ldc D:/Avant_Versa_RevB/Avant-X Versa Board revB_Blink/impl_1/Blink_RevB_impl_1.ldc -gui -msgset D:/Avant_Versa_RevB/Avant-X Versa Board revB_Blink/promote.xml Blink_RevB_impl_1.vm
       Architecture:     LAV-AT
       Device:           LAV-AT-X70
       Package:          LFG1156
       Performance:      3
    Reading input file 'Blink_RevB_impl_1.vm' ...
    Reading constraint file 'D:/Avant_Versa_RevB/Avant-X Versa Board revB_Blink/impl_1/Blink_RevB_impl_1.ldc' ...
    Removing unused logic ...
    Starting design annotation....
    WARNING <70001944> - No source clock for
    	generated clock	create_generated_clock -name {clk_25[0]} -source [get_pins {pll_inst/lscc_pll_inst/gen_ext_outclkdiv.gen_no_clk7.u_pll.PLLC_MODE_inst/CLKI}] -divide_by 4 [get_pins {pll_inst/lscc_pll_inst/gen_ext_outclkdiv.gen_no_clk7.u_pll.PLLC_MODE_inst/CLKOP }] .

    Constraint Summary:
       Total number of constraints: 1
       Total number of constraints dropped: 0

    Writing output file 'Blink_RevB_impl_1_syn.udb'.
    POSTSYN finished successfully.
    Total CPU Time: 3 secs
    Total REAL Time: 4 secs
    Peak Memory Usage: 771 MB
    Checksum -- postsyn: 5360bdc053e544d9eafc336076636dbdfa215405