    Copyright (c) 2002-2022 Lattice Semiconductor Corporation,  All rights reserved.

    Thu Mar 14 15:42:32 2024

    Command Line: par -w -n 1 -t 1 -s 1 -cores 1 -hsp m Blink_RevB_impl_1_map.udb \
    	Blink_RevB_impl_1.udb

    Cost Table Summary
    Level/       Number       Estimated       Timing       Estimated Worst    Timing          Run      Run
    Cost [udb]   Unrouted     Worst Slack     Score        Slack(hold)        Score(hold)     Time     Status
    ----------   --------     -----------     ------       ---------------    -----------     ----     ------
    5_1   *      0            -               0            -                  0               01:28    Completed
    * : Design saved.

    Total (real) run time for 1-seed: 1 mins 40 secs

    par done!

    Lattice Place and Route Report for Design "Blink_RevB_impl_1_map.udb"
    Thu Mar 14 15:42:32 2024

    Best Par Run
    PAR: Place And Route Radiant Software (64-bit) 2023.2.t.305.0.
    Command Line: par -w -t 1 -cores 1 -hsp m Blink_RevB_impl_1_map.udb \
    	Blink_RevB_impl_1_par.dir/5_1.udb

    Loading Blink_RevB_impl_1_map.udb ...
    Loading device for application GENERIC from file 'ap6a400b.nph' in environment: D:/radiant/2023.2.305/ispfpga.
    Package Status:                     Advanced       Version 28.
    Performance Hardware Data Status:   Advanced       Version 68.1.

    Design:  blink_top
    Family:  LAV-AT
    Device:  LAV-AT-X70
    Package: LFG1156
    Performance Grade:   3
    WARNING <71301018> - par: The PLL clock port [clk_in] is assigned to a non PLL dedicated pin [T7], which might affect the clock performance. Use dedicated PLL clock resources for the port.
    WARNING <70001944> - par: No source clock for
    	generated clock	create_generated_clock -name {clk_25[0]} -source [get_pins {pll_inst/lscc_pll_inst/gen_ext_outclkdiv.gen_no_clk7.u_pll.PLLC_MODE_inst/CLKI}] -divide_by 4 [get_pins {pll_inst/lscc_pll_inst/gen_ext_outclkdiv.gen_no_clk7.u_pll.PLLC_MODE_inst/CLKOP }] .
    Number of Signals: 127
    Number of Connections: 319

    +
    Pin Constraint Summary:
       16 out of 16 pins locked (100% locked).

    Starting Placer Phase 0. CPU time: 35 secs , REAL time: 40 secs

    Finished Placer Phase 0. CPU time: 35 secs , REAL time: 40 secs

    Starting Placer Phase 1. CPU time: 35 secs , REAL time: 40 secs

    Finished Placer Phase 1. CPU time: 35 secs , REAL time: 40 secs

    Placer score = 1781.
    Starting Placer Phase 2. CPU time: 35 secs , REAL time: 40 secs

    Finished Placer Phase 2. CPU time: 35 secs , REAL time: 40 secs

    Placer score =  1763

    Device utilization summary:

       WRIO                 16/99           16% used
                            16/99           16% bonded
       PLL                   1/11            9% used
       SLICE                39/198720       <1% used
         LUT                75/397440       <1% used
         REG                32/397440       <1% used

    Clock Report

    Global Clock Resources:
      CLK_PIN    : 0 out of 22 (0%)
      PLL        : 1 out of 11 (9%)
      DCS        : 0 out of 4 (0%)
      DCC        : 0 out of 344 (0%)
      ECLKDIV    : 0 out of 45 (0%)
      OSC        : 0 out of 1 (0%)

    Global Clocks:
      PRIMARY "clk_25[0]" from CLKOP on comp "pll_inst.lscc_pll_inst.gen_ext_outclkdiv.gen_no_clk7.u_pll.PLLC_MODE_inst" on PLL site "PLL11", clk load = 21, ce load = 0, sr load = 0

      PRIMARY  : 1 out of 24 (4%)

    Edge Clocks:
      No edge clock selected.

    I/O Usage Summary (final):
       16 out of 95 (16.8%) WRIO sites used.
       16 out of 95 (16.8%) bonded WRIO sites used.
       Number of WRIO components: 16; differential: 0
       Number of Vref pins used: 0
       0 out of 468 (0.0%) HPIO sites used.
       0 out of 468 (0.0%) bonded HPIO sites used.
       Number of HPIO components: 0; differential: 0

    I/O Bank Usage Summary:
    +----------+----------------+------------+------------+
    | I/O Bank | Usage          | Bank Vccio | Bank Vref1 |
    +----------+----------------+------------+------------+
    | 0        | 1 / 16 (  6%)  | 3.3V       | -          |
    | 1        | 0 / 15 (  0%)  | -          | -          |
    | 2        | 0 / 12 (  0%)  | -          | -          |
    | 3        | 0 / 52 (  0%)  | -          | -          |
    | 4        | 0 / 52 (  0%)  | -          | -          |
    | 5        | 0 / 52 (  0%)  | -          | -          |
    | 6        | 0 / 52 (  0%)  | -          | -          |
    | 7        | 0 / 52 (  0%)  | -          | -          |
    | 8        | 0 / 52 (  0%)  | -          | -          |
    | 9        | 0 / 52 (  0%)  | -          | -          |
    | 10       | 0 / 52 (  0%)  | -          | -          |
    | 11       | 0 / 52 (  0%)  | -          | -          |
    | 12       | 0 / 16 (  0%)  | -          | -          |
    | 13       | 15 / 16 ( 93%) | 3.3V       | -          |
    | 14       | 0 / 20 (  0%)  | -          | -          |
    +----------+----------------+------------+------------+

    Total Placer CPU time: 36 secs , REAL time: 41 secs

    Checksum -- place: f54798693d596314ebf3a6014d63102df61714c7
    Writing design to file Blink_RevB_impl_1_par.dir/5_1.udb ...

    WARNING <71301018> - par: The PLL clock port [clk_in] is assigned to a non PLL dedicated pin [T7], which might affect the clock performance. Use dedicated PLL clock resources for the port.

    Start NBR router at 15:43:21 03/14/24

    *****************************************************************
    Info: NBR allows conflicts(one node used by more than one signal)
          in the earlier iterations. In each iteration, it tries to
          solve the conflicts while keeping the critical connections
          routed as short as possible. The routing process is said to
          be completed when no conflicts exist and all connections
          are routed.
    Note: NBR uses a different method to calculate timing slacks. The
          worst slack and total negative slack may not be the same as
          that in timing report. You should always run the timing
          tool to verify your design.
    *****************************************************************

    Starting routing resource preassignment
    Preassignment Summary:
    --------------------------------------------------------------------------------
    43 connections routed with dedicated routing resources
    1 global clock signals routed
    64 connections routed (of 298 total) (21.48%)
    ---------------------------------------------------------
    Clock routing summary:
    Global clocks (1 used out of 24 available):
        Signal "clk_25[0]"
           Clock   loads: 21    out of    21 routed (100.00%)
    Other clocks:
        Signal "clk_in_c"
           Clock   loads: 0     out of     1 routed (  0.00%)
    ---------------------------------------------------------
    --------------------------------------------------------------------------------
    Completed routing resource preassignment
    WARNING <70001944> - par: No source clock for
    	generated clock	create_generated_clock -name {clk_25[0]} -source [get_pins {pll_inst/lscc_pll_inst/gen_ext_outclkdiv.gen_no_clk7.u_pll.PLLC_MODE_inst/CLKI}] -divide_by 4 [get_pins {pll_inst/lscc_pll_inst/gen_ext_outclkdiv.gen_no_clk7.u_pll.PLLC_MODE_inst/CLKOP }] .
    +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
    Routing in Serial Mode ......
    +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    Start NBR section for initial routing at 15:43:55 03/14/24
    Level 4, iteration 1
    6(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 0 (nbr) score; real time: 35 secs

    Info: Initial congestion level at 75.00% usage is 0
    Info: Initial congestion area  at 75.00% usage is 0 (0.00%)

    Start NBR section for normal routing at 15:43:57 03/14/24
    Level 4, iteration 1
    1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 0 (nbr) score; real time: 36 secs
    Level 4, iteration 2
    0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 0 (nbr) score; real time: 36 secs

    Start NBR section for post-routing at 15:43:57 03/14/24

    End NBR router with 0 unrouted connection

    Checksum -- route: 63f14c2b4f9792a93b1b92cdc91432abd7401674

    Total CPU time 36 secs
    Total REAL time: 37 secs
    Completely routed.
    End of route.  298 routed (100.00%); 0 unrouted.

    Writing design to file Blink_RevB_impl_1_par.dir/5_1.udb ...

    All signals are completely routed.

    PAR_SUMMARY::Run status = Completed
    PAR_SUMMARY::Number of unrouted conns = 0
    PAR_SUMMARY::Estimated worst slack<setup/<ns>> = <n/a>
    PAR_SUMMARY::Timing score<setup/<ns>> = <n/a>
    PAR_SUMMARY::Estimated worst slack<hold/<ns>> = <n/a>
    PAR_SUMMARY::Timing score<hold/<ns>> = <n/a>
    PAR_SUMMARY::Number of errors = 0

    Note: user must run 'timing' for timing closure signoff.

    Total CPU  Time: 1 mins 35 secs
    Total REAL Time: 1 mins 40 secs
    Peak Memory Usage: 7667.84 MB

    par done!

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2023 Lattice Semiconductor Corporation,  All rights reserved.