    Setting log file to '//lshitd0046/Hardware_share/Avant_test_board_test_files/RevB/Avant-X Versa Board revB_Blink/impl_1/hdla_gen_hierarchy.html'.
    Starting: parse design source files
    (VERI-1482) Analyzing Verilog file 'D:/radiant/2023.2.305/cae_library/synthesis/verilog/lav-atx.v'
    (VERI-1482) Analyzing Verilog file '//lshitd0046/Hardware_share/Avant_test_board_test_files/RevB/Avant-X Versa Board revB_Blink/source/impl_1/blink_top.v'
    WARNING <2049991> - //lshitd0046/Hardware_share/Avant_test_board_test_files/RevB/Avant-X Versa Board revB_Blink/source/impl_1/blink_top.v(95,4-95,17) (VERI-1988) empty statement in sequential block
    WARNING <2049991> - //lshitd0046/Hardware_share/Avant_test_board_test_files/RevB/Avant-X Versa Board revB_Blink/source/impl_1/blink_top.v(99,4-99,17) (VERI-1988) empty statement in sequential block
    WARNING <2049991> - //lshitd0046/Hardware_share/Avant_test_board_test_files/RevB/Avant-X Versa Board revB_Blink/source/impl_1/blink_top.v(103,4-103,17) (VERI-1988) empty statement in sequential block
    WARNING <2049991> - //lshitd0046/Hardware_share/Avant_test_board_test_files/RevB/Avant-X Versa Board revB_Blink/source/impl_1/blink_top.v(107,4-107,17) (VERI-1988) empty statement in sequential block
    WARNING <2049991> - //lshitd0046/Hardware_share/Avant_test_board_test_files/RevB/Avant-X Versa Board revB_Blink/source/impl_1/blink_top.v(111,4-111,17) (VERI-1988) empty statement in sequential block
    WARNING <2049991> - //lshitd0046/Hardware_share/Avant_test_board_test_files/RevB/Avant-X Versa Board revB_Blink/source/impl_1/blink_top.v(115,4-115,17) (VERI-1988) empty statement in sequential block
    WARNING <2049991> - //lshitd0046/Hardware_share/Avant_test_board_test_files/RevB/Avant-X Versa Board revB_Blink/source/impl_1/blink_top.v(119,4-119,17) (VERI-1988) empty statement in sequential block
    WARNING <2049991> - //lshitd0046/Hardware_share/Avant_test_board_test_files/RevB/Avant-X Versa Board revB_Blink/source/impl_1/blink_top.v(123,4-123,17) (VERI-1988) empty statement in sequential block
    WARNING <2049991> - //lshitd0046/Hardware_share/Avant_test_board_test_files/RevB/Avant-X Versa Board revB_Blink/source/impl_1/blink_top.v(127,4-127,17) (VERI-1988) empty statement in sequential block
    WARNING <2049991> - //lshitd0046/Hardware_share/Avant_test_board_test_files/RevB/Avant-X Versa Board revB_Blink/source/impl_1/blink_top.v(131,4-131,17) (VERI-1988) empty statement in sequential block
    (VERI-1482) Analyzing Verilog file '//lshitd0046/Hardware_share/Avant_test_board_test_files/RevB/Avant-X Versa Board revB_Blink/pll_H/rtl/pll_H.v'
    INFO <2049992> - //lshitd0046/Hardware_share/Avant_test_board_test_files/RevB/Avant-X Versa Board revB_Blink/source/impl_1/blink_top.v(19,8-19,17) (VERI-1018) compiling module 'blink_top'
    Done: design load finished with (0) errors, and (10) warnings