@W: BN132 :"d:\avant_versa_revb\avant-x versa board revb_blink\source\impl_1\blink_top.v":67:0:67:5|Removing sequential instance cnt_0[27:0] because it is equivalent to instance cnt[27:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN137 :|Found combinational loop during mapping at net lat_5
@W: BN137 :|Found combinational loop during mapping at net lat_4
@W: BN137 :|Found combinational loop during mapping at net lat_3
@W: BN137 :|Found combinational loop during mapping at net lat_2
@W: BN137 :|Found combinational loop during mapping at net lat_1
@W: BN137 :|Found combinational loop during mapping at net lat_0
@W: BN137 :|Found combinational loop during mapping at net lat
@W: BN137 :|Found combinational loop during mapping at net lat_5
@W: BN137 :|Found combinational loop during mapping at net lat_4
@W: BN137 :|Found combinational loop during mapping at net lat_3
@W: BN137 :|Found combinational loop during mapping at net lat_2
@W: BN137 :|Found combinational loop during mapping at net lat_1
@W: BN137 :|Found combinational loop during mapping at net lat_0
@W: BN137 :|Found combinational loop during mapping at net lat
@W: MT246 :"d:\avant_versa_revb\avant-x versa board revb_blink\pll_h\rtl\pll_h.v":1480:63:1480:67|Blackbox PLLC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock pll_H_ipgen_lscc_pll_Z1_layer0|clkout_clkop_o_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll_inst.lscc_pll_inst.clk_25[0].
@W: MT420 |Found inferred clock blink_top|un1_seg21_inferred_clock with period 5.00ns. Please declare a user-defined clock on net I_37.lat_e.
