Timing Report
Lattice Timing Report - Setup and Hold, Version Radiant Software (64-bit) 2023.2.t.305.0
Thu Mar 14 15:44:35 2024
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
Command line: timing -sethld -v 10 -u 10 -endpoints 10 -nperend 1 -sp 3 -hsp m -pwrprd -html -rpt Blink_RevB_impl_1.twr Blink_RevB_impl_1.udb -gui -msgset D:/Avant_Versa_RevB/Avant-X Versa Board revB_Blink/promote.xml
------------------------------
Design: blink_top
Family: LAV-AT
Device: LAV-AT-X70
Package: LFG1156
Performance: 3
Package Status: Advanced Version 28
Performance Hardware Data Status : Advanced Version 68.1
------------------------------
=====================================================================
Table of Contents
=====================================================================
1 Timing Overview
1.1 SDC Constraints
1.2 Constraint Coverage
1.3 Overall Summary
1.4 Unconstrained Report
1.5 Combinational Loop
1.6 Error/Warning Messages
2 Setup at Speed Grade 3 Corner at 85 Degrees
2.1 Clock Summary
2.2 Endpoint slacks
2.3 Detailed Report
3 Setup at Speed Grade 3 Corner at 0 Degrees
3.1 Clock Summary
3.2 Endpoint slacks
3.3 Detailed Report
4 Hold at Speed Grade m Corner at 0 Degrees
4.1 Endpoint slacks
4.2 Detailed Report
=====================================================================
End of Table of Contents
=====================================================================
1 Timing Overview
1.1 SDC Constraints
[IGNORED:]create_generated_clock -name {clk_25[0]} -source [get_pins pll_inst.lscc_pll_inst.gen_ext_outclkdiv.gen_no_clk7.u_pll.PLLC_MODE_inst/REFCLK] -divide_by 4 [get_pins pll_inst.lscc_pll_inst.gen_ext_outclkdiv.gen_no_clk7.u_pll.PLLC_MODE_inst/CLKOP]
1.2 Constraint Coverage
Constraint Coverage: 0%
1.3 Overall Summary
Setup at Speed Grade 3 Corner at 85 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns
Setup at Speed Grade 3 Corner at 0 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns
Hold at Speed Grade m Corner at 0 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns
1.4 Unconstrained Report
1.4.1 Unconstrained Start/End Points
Clocked but unconstrained timing start points
--------------------------------------------------
There is no start point satisfying reporting criteria
Clocked but unconstrained timing end points
-------------------------------------------------------------------
Listing 10 End Points | Type
-------------------------------------------------------------------
cnt_Z[27]/DF | No arrival or required
cnt_Z[26]/DF | No arrival or required
{cnt_Z[27]/LSR cnt_Z[26]/LSR} | No arrival or required
cnt_Z[25]/DF | No arrival or required
cnt_Z[25]/LSR | No arrival or required
cnt_Z[23]/DF | No arrival or required
cnt_Z[23]/LSR | No arrival or required
cnt_Z[17]/DF | No arrival or required
cnt_Z[17]/LSR | No arrival or required
cnt_Z[15]/DF | No arrival or required
-------------------------------------------------------------------
|
Number of unconstrained timing end poin |
ts | 50
|
-------------------------------------------------------------------
1.4.2 Start/End Points Without Timing Constraints
I/O ports without constraint
----------------------------
Possible constraints to use on I/O ports are:
set_input_delay,
set_output_delay,
set_max_delay,
create_clock,
create_generated_clock,
...
-------------------------------------------------------------------
Listing 10 Start or End Points | Type
-------------------------------------------------------------------
clk_in | input
sw12 | input
sw13 | input
sw14 | input
sw15 | input
seg1 | output
seg2 | output
seg3 | output
seg_a | output
seg_b | output
-------------------------------------------------------------------
|
Number of I/O ports without constraint | 15
|
-------------------------------------------------------------------
Nets without clock definition
Define a clock on a top level port or a generated clock on a clock divider pin associated with this net(s).
--------------------------------------------------
There is no instance satisfying reporting criteria
1.5 Combinational Loop
Combinational Loops
-------------------
++++ Loop1
I_41.lat/B -> I_41.lat/Z
++++ Loop2
I_37.lat/B -> I_37.lat/Z
++++ Loop3
I_40.lat/B -> I_40.lat/Z
++++ Loop4
I_42.lat/B -> I_42.lat/Z
++++ Loop5
I_39.lat/C -> I_39.lat/Z
++++ Loop6
I_38.lat/B -> I_38.lat/Z
++++ Loop7
I_43.lat/B -> I_43.lat/Z
1.6 Error/Warning Messages
WARNING "70001944" - No source clock for
generated clock create_generated_clock -name {clk_25[0]} -source [get_pins {pll_inst/lscc_pll_inst/gen_ext_outclkdiv.gen_no_clk7.u_pll.PLLC_MODE_inst/CLKI}] -divide_by 4 [get_pins {pll_inst/lscc_pll_inst/gen_ext_outclkdiv.gen_no_clk7.u_pll.PLLC_MODE_inst/CLKOP }] .
2 Setup at Speed Grade 3 Corner at 85 Degrees
2.1 Clock Summary
2.1.1 Clock "clk_25[0]"
create_generated_clock -name {clk_25[0]} -source [get_pins {pll_inst/lscc_pll_inst/gen_ext_outclkdiv.gen_no_clk7.u_pll.PLLC_MODE_inst/CLKI}] -divide_by 4 [get_pins {pll_inst/lscc_pll_inst/gen_ext_outclkdiv.gen_no_clk7.u_pll.PLLC_MODE_inst/CLKOP }]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock clk_25[0] | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From clk_25[0] | Target | +INF | 0.000 MHz
| Actual (all paths) | 1.600 ns | 625.000 MHz
{cnt_Z[27]/CLK cnt_Z[26]/CLK} (MPW) | (50% duty cycle) | 1.600 ns | 625.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
2.2 Endpoint slacks
--------------------------------------------------
There is no end point satisfying reporting criteria
Total Negative Slack: 0
2.3 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
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+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
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End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################
3 Setup at Speed Grade 3 Corner at 0 Degrees
3.1 Clock Summary
3.1.1 Clock "clk_25[0]"
create_generated_clock -name {clk_25[0]} -source [get_pins {pll_inst/lscc_pll_inst/gen_ext_outclkdiv.gen_no_clk7.u_pll.PLLC_MODE_inst/CLKI}] -divide_by 4 [get_pins {pll_inst/lscc_pll_inst/gen_ext_outclkdiv.gen_no_clk7.u_pll.PLLC_MODE_inst/CLKOP }]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock clk_25[0] | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From clk_25[0] | Target | +INF | 0.000 MHz
| Actual (all paths) | 1.600 ns | 625.000 MHz
{cnt_Z[27]/CLK cnt_Z[26]/CLK} (MPW) | (50% duty cycle) | 1.600 ns | 625.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
3.2 Endpoint slacks
--------------------------------------------------
There is no end point satisfying reporting criteria
Total Negative Slack: 0
3.3 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################
4 Hold at Speed Grade m Corner at 0 Degrees
4.1 Endpoint slacks
--------------------------------------------------
There is no end point satisfying reporting criteria
Total Negative Slack: 0
4.2 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################