Lattice Mapping Report File Design: blink_top Family: LAV-AT Device: LAV-AT-X70 Package: LFG1156 Performance Grade: 3 Mapper: version Radiant Software (64-bit) 2024.1.t.30.0 Mapped on: Mon Feb 19 09:56:33 2024 Design Information Command line: map -i Blink_RevB_impl_1_syn.udb -pdc D:/Avant_Versa_RevB/Avant-X Versa Board revB_Blink/pinout.pdc -o Blink_RevB_impl_1_map.udb -mp Blink_RevB_impl_1.mrp -hierrpt -gui -msgset D:/Avant_Versa_RevB/Avant-X Versa Board revB_Blink/promote.xml Design Summary Number of registers: 32 out of 399111 (<1%) Number of SLICE registers: 32 out of 397440 (<1%) Number of PIO Input registers: 0 out of 557 (0%) Number of PIO Output registers: 0 out of 557 (0%) Number of PIO Tri-State registers: 0 out of 557 (0%) Number of LUT4s: 75 out of 397440 (<1%) Number used as logic LUT4s: 47 Number used as distributed RAM: 0 (6 per 16X4 or 32X2 RAM) Number used as ripple logic: 28 (2 per CCU2) Number of PIOs used/reserved: 24 out of 557 (4%) Number of wide range IOs used/reserved: 24 out of 98 (24%) Number of high performance IOs used/reserved: 0 out of 459 (0%) Number of generic IOs used: 0 (either wide range or high performance) Number of wide range IOs reserved: 8 (per sysConfig/prohibit constraint) Number of IOs used: 16 Number used for single ended IO: 16 Number of pairs used for differential IO: 0 Number allocated to wide range IOs: 16 out of 98 (16%) Number allocated to high performance IOs: 0 out of 459 (0%) (either wide range or high performance) Number of Dedicated IO used for MPPHYX4/MPPCIEX8: 0 out of 126 (0%) Number of IDDR/ODDR functions used: 0 out of 1114 (0%) Number of IOs using at least one DDR function: 0 (0 differential) Minimum Number of 32K Block RAMs: 0 out of 990 (0%) Minimum Number of DSP Blocks: 0 out of 1800 (0%) Number of PLLs: 1 out of 11 (9%) Number of DDRDLLs: 0 out of 13 (0%) Number of DLLDELs: 0 out of 44 (0%) Number of DCSs: 0 out of 4 (0%) Number of DCCs: 0 out of 344 (0%) Number of ECLKDIVs: 0 out of 45 (0%) Number of ECLKSYNCs: 0 out of 54 (0%) Number of Multi-Protocol Quads: 0 out of 7 (0%) Number of DDRPHYs: 0 out of 3 (0%) Number of Oscillators: 0 out of 1 (0%) Number of GSR: 0 out of 1 (0%) Number of Cryptographic Block: 0 out of 1 (0%) Number of TSALL: 0 out of 1 (0%) Number of JTAG: 0 out of 1 (0%) Number of LMMI Slave: 0 out of 1 (0%) Number of SED: 0 out of 1 (0%) Number of Config WDT: 0 out of 1 (0%) Number of Clocks: 2 Net clk_25[0]: 32 loads, 32 rising, 0 falling (Driver: Pin pll_inst.lscc_p ll_inst.gen_ext_outclkdiv.gen_no_clk7.u_pll.PLLC_MODE_inst/CLKOP) Net clk_in_c: 1 loads, 1 rising, 0 falling (Driver: Port clk_in) Number of Clock Enables: 0 Number of LSRs: 1 Pin sw12: 29 loads, 28 SLICEs (Net: sw12_c) Top 10 highest fanout non-clock nets: Net sw12_c: 32 loads Net cnt8_20: 15 loads Net cnt8_21: 15 loads Net cnt8_25: 15 loads Net wei[0]: 13 loads Net wei[1]: 13 loads Net wei[2]: 12 loads Net wei[3]: 8 loads Net I_37.lat_e: 7 loads Net cnt8: 4 loads Number of warnings: 16 Number of errors: 0 Design Errors/Warnings WARNING <1026001> - map: D:/Avant_Versa_RevB/Avant-X Versa Board revB_Blink/pinout.pdc (2) : No port matched 'led[0]'. WARNING <1026001> - map: D:/Avant_Versa_RevB/Avant-X Versa Board revB_Blink/pinout.pdc (3) : No port matched 'led[1]'. WARNING <1026001> - map: D:/Avant_Versa_RevB/Avant-X Versa Board revB_Blink/pinout.pdc (4) : No port matched 'led[2]'. WARNING <1027013> - map: No port matched 'led[0]'. WARNING <1014301> - map: Can't resolve object 'led[0]' in constraint 'ldc_set_location -site {AN10} [get_ports {led[0]}]'. WARNING <1027013> - map: No port matched 'led[1]'. WARNING <1014301> - map: Can't resolve object 'led[1]' in constraint 'ldc_set_location -site {AH13} [get_ports {led[1]}]'. WARNING <1027013> - map: No port matched 'led[2]'. WARNING <1014301> - map: Can't resolve object 'led[2]' in constraint 'ldc_set_location -site {AJ13} [get_ports {led[2]}]'. WARNING <1011001> - map: Remove invalid constraint 'ldc_set_location -site {AN10} [get_ports {led[0]}]'. WARNING <1011001> - map: Remove invalid constraint 'ldc_set_location -site {AH13} [get_ports {led[1]}]'. WARNING <1011001> - map: Remove invalid constraint 'ldc_set_location -site {AJ13} [get_ports {led[2]}]'. CRITICAL <52351080> - map: SysConfig constraint CONFIGIO_VOLTAGE_BANK1 is not specified. Please set it to 1.2, 1.8, 2.5 or 3.3. CRITICAL <52351080> - map: SysConfig constraint CONFIGIO_VOLTAGE_BANK2 is not specified. Please set it to 1.2, 1.8, 2.5 or 3.3. CRITICAL <52351079> - map: There is no set_clock_uncertainty constraint on the PLL clock output 'CLKOP' of instance 'pll_inst/lscc_pll_inst/gen_ext_outclk div.gen_no_clk7.u_pll.PLLC_MODE_inst'. Please see FPGA-AN-02059-1.0 - Lattice Radiant Timing Constraints Methodology for further details. WARNING <71301018> - map: The PLL clock port [clk_in] is assigned to a non PLL dedicated pin [T7], which might affect the clock performance. Use dedicated PLL clock resources for the port. IO (PIO) Attributes +---------------------+-----------+-----------+-------+-------+-----------+ | IO Name | Direction | Levelmode | IO | IO | Special | | | | IO_TYPE | REG | DDR | IO Buffer | +---------------------+-----------+-----------+-------+-------+-----------+ | clk_in | INPUT | LVCMOS33 | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | sw12 | INPUT | LVCMOS33 | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | sw13 | INPUT | LVCMOS33 | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | sw14 | INPUT | LVCMOS33 | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | sw15 | INPUT | LVCMOS33 | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | seg1 | OUTPUT | LVCMOS33 | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | seg2 | OUTPUT | LVCMOS33 | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | seg3 | OUTPUT | LVCMOS33 | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | seg_a | OUTPUT | LVCMOS33 | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | seg_b | OUTPUT | LVCMOS33 | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | seg_c | OUTPUT | LVCMOS33 | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | seg_d | OUTPUT | LVCMOS33 | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | seg_e | OUTPUT | LVCMOS33 | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | seg_f | OUTPUT | LVCMOS33 | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | seg_g | OUTPUT | LVCMOS33 | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | seg_dp | OUTPUT | LVCMOS33 | | | | +---------------------+-----------+-----------+-------+-------+-----------+ Removed logic Block GSR_INST undriven or does not drive anything - clipped. Block GND_cZ was optimized away. Block sw12_ibuf_RNII395 was optimized away. Block VCC_cZ was optimized away. PLL/DLL Summary --------------- PLL 1: Pin/Node Value PLL Instance Name: pll_inst/lscc_pll_inst/gen_ext_o utclkdiv.gen_no_clk7.u_pll.PLLC_MODE_inst Input Reference Clock: PIN clk_in_c Output Clock(P): NODE clk_25[0] Output Clock(S): NONE Output Clock(S2): NONE Output Clock(S3): NONE Output Clock(S4): NONE Output Clock(S5): NONE Output Clock(PHY): NONE Feedback Signal: NONE PLL LOCK signal: PIN seg_dp_c CLKI Divider: 1 CLKFB Divider: 40 CLKOP Divider: 160 CLKOP CPHASE: 160 CLKOP FPHASE: 1 CLKOS Divider: 1 CLKOS CPHASE: 1 CLKOS FPHASE: 1 CLKOS2 Divider: 1 CLKOS2 CPHASE: 1 CLKOS2 FPHASE: 1 CLKOS3 Divider: 1 CLKOS3 CPHASE: 1 CLKOS3 FPHASE: 1 CLKOS4 Divider: 1 CLKOS4 CPHASE: 1 CLKOS4 FPHASE: 1 CLKOS5 Divider: 1 CLKOS5 CPHASE: 1 CLKOS5 FPHASE: 1 CLKPHY Divider: 1 CLKPHY FPHASE: 1 ASIC Components --------------- Instance Name: pll_inst/lscc_pll_inst/gen_ext_outclkdiv.gen_no_clk7.u_pll.PLLC_MODE_inst Type: PLL_CORE Constraint Summary ------------------ Total number of constraints: 37 Total number of constraints dropped: 3 Dropped constraints are: ldc_set_location -site {AN10} [get_ports {led[0]}] ldc_set_location -site {AH13} [get_ports {led[1]}] ldc_set_location -site {AJ13} [get_ports {led[2]}] Run Time and Memory Usage ------------------------- Total CPU Time: 26 secs Total REAL Time: 28 secs Peak Memory Usage: 92 MB Checksum -- map: cdd966523033fc8692f3aa886c5979127eebd752 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.