@W: CG360 :"D:\Avant_Versa_RevB\Avant-X Versa Board revB_Blink\pll_H\rtl\pll_H.v":314:16:314:31|Removing wire clkout_testclk_o, as there is no assignment to it.
@W: CG360 :"D:\Avant_Versa_RevB\Avant-X Versa Board revB_Blink\pll_H\rtl\pll_H.v":322:16:322:36|Removing wire outresetack_testclk_o, as there is no assignment to it.
@W: CG360 :"D:\Avant_Versa_RevB\Avant-X Versa Board revB_Blink\pll_H\rtl\pll_H.v":334:16:334:32|Removing wire stepack_testclk_o, as there is no assignment to it.
@W: CG360 :"D:\Avant_Versa_RevB\Avant-X Versa Board revB_Blink\pll_H\rtl\pll_H.v":357:16:357:27|Removing wire apb_pready_o, as there is no assignment to it.
@W: CG360 :"D:\Avant_Versa_RevB\Avant-X Versa Board revB_Blink\pll_H\rtl\pll_H.v":358:16:358:28|Removing wire apb_pslverr_o, as there is no assignment to it.
@W: CG360 :"D:\Avant_Versa_RevB\Avant-X Versa Board revB_Blink\pll_H\rtl\pll_H.v":359:23:359:34|Removing wire apb_prdata_o, as there is no assignment to it.
@W: CL318 :"D:\Avant_Versa_RevB\Avant-X Versa Board revB_Blink\pll_H\rtl\pll_H.v":314:16:314:31|*Output clkout_testclk_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Avant_Versa_RevB\Avant-X Versa Board revB_Blink\pll_H\rtl\pll_H.v":322:16:322:36|*Output outresetack_testclk_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Avant_Versa_RevB\Avant-X Versa Board revB_Blink\pll_H\rtl\pll_H.v":334:16:334:32|*Output stepack_testclk_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Avant_Versa_RevB\Avant-X Versa Board revB_Blink\pll_H\rtl\pll_H.v":357:16:357:27|*Output apb_pready_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Avant_Versa_RevB\Avant-X Versa Board revB_Blink\pll_H\rtl\pll_H.v":358:16:358:28|*Output apb_pslverr_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Avant_Versa_RevB\Avant-X Versa Board revB_Blink\pll_H\rtl\pll_H.v":359:23:359:34|*Output apb_prdata_o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL118 :"D:\Avant_Versa_RevB\Avant-X Versa Board revB_Blink\source\impl_1\blink_top.v":92:1:92:4|Latch generated from always block for signal seg[6:0]; possible missing assignment in an if or case statement.

