@N: MF472 |Synthesis running in Automatic Compile Point mode
@N: MF474 |No compile point is identified in Automatic Compile Point mode
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: MO111 :"d:\avant_versa_revb\avant-x versa board revb_blink\pll_h\rtl\pll_h.v":359:23:359:34|Tristate driver apb_prdata_o_1 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_1 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\avant_versa_revb\avant-x versa board revb_blink\pll_h\rtl\pll_h.v":359:23:359:34|Tristate driver apb_prdata_o_2 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_2 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\avant_versa_revb\avant-x versa board revb_blink\pll_h\rtl\pll_h.v":359:23:359:34|Tristate driver apb_prdata_o_3 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_3 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\avant_versa_revb\avant-x versa board revb_blink\pll_h\rtl\pll_h.v":359:23:359:34|Tristate driver apb_prdata_o_4 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_4 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\avant_versa_revb\avant-x versa board revb_blink\pll_h\rtl\pll_h.v":359:23:359:34|Tristate driver apb_prdata_o_5 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_5 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\avant_versa_revb\avant-x versa board revb_blink\pll_h\rtl\pll_h.v":359:23:359:34|Tristate driver apb_prdata_o_6 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_6 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\avant_versa_revb\avant-x versa board revb_blink\pll_h\rtl\pll_h.v":359:23:359:34|Tristate driver apb_prdata_o_7 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_7 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\avant_versa_revb\avant-x versa board revb_blink\pll_h\rtl\pll_h.v":359:23:359:34|Tristate driver apb_prdata_o_8 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_8 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\avant_versa_revb\avant-x versa board revb_blink\pll_h\rtl\pll_h.v":359:23:359:34|Tristate driver apb_prdata_o_9 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_9 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\avant_versa_revb\avant-x versa board revb_blink\pll_h\rtl\pll_h.v":359:23:359:34|Tristate driver apb_prdata_o_10 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) on net apb_prdata_o_10 (in view: work.pll_H_ipgen_lscc_pll_Z1_layer0(verilog)) has its enable tied to GND.
@N: FX1184 |Applying syn_allowed_resources blockrams=990 on top level netlist blink_top 
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
