The Lattice Double Data Rate Synchronous Dynamic Random Access Memory (DDR3 SDRAM) Controller IP Core is a general-purpose memory controller that interfaces with industry standard DDR3 memory devices compliant with JESD79-3C, DDR3 SDRAM Standard. This IP provides a generic command interface to user applications.
This IP supports the following Nexus devices in Lattice Radiant: CrossLink™-NX, Certus™-NX, Mach™-NX, and CertusPro™-NX. It also supports the ECP5 and LatticeECP3 devices in Lattice Diamond.
Resource Utilization details are available in the DDR3 SDRAM Controller (Lattice Radiant) and DDR3 SDRAM Controller (Lattice Diamond) User Guides.
Features
Nexus
- Memory data path widths of 8, 16, 24, 32, 40, 48, 56, 64, and 72 bits.
- x4, x8, and x16 device configurations
- Interfaces to DDR3 SDRAM at speeds of up to 400 MHz/800 Mbps in speed grade 8 ECP5 devices and speed grade 9 LatticeECP3 devices
- Programmable burst lengths of 8 (fixed), chopped 4 or 8 (on-the-fly), or chopped 4 (fixed)
- x8 and x16 device configurations
- Programmable burst lengths of 8 (fixed), chopped 4 or 8 (on-the-fly), or chopped 4 (fixed)
ECP5 and LatticeECP3
- Memory data path widths of 8, 16, 24, 32, 40, 48, 56, 64, and 72 bits
- x4, x8, and x16 device configurations
- Interfaces to DDR3 SDRAM at speeds of up to 400 MHz/800 Mbps in speed grade 8 ECP5 devices and speed grade 9 LatticeECP3 devices
- Programmable burst lengths of 8 (fixed), chopped 4 or 8 (on-the-fly), or chopped 4 (fixed)
