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Certus-NX

Low-Power General Purpose FPGA

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Industry-leading I/O Count in Small Packages – Up to 2x more I/O per mm2 vs. similar FPGAs, in packages as small as 6x6 mm, with support for PCIe and GigE.

High-speed Interfaces – Up to 70% faster differential I/O (vs. similar FPGAs) at 1.5 Gbps. 5 Gbps PCIe, 1 Gbps GigE and 1066 Mbps DDR3 memory interfaces also supported.

Built on Lattice Nexus platform – Up to 4x lower power vs. similar FPGAs. Up to 100x higher reliability, due to 100x lower Soft Error Rate (SER) from 28 nm FD-SOI technology. Extended density range and features available in the CertusPro-NX family.

Certus-NX

Features

  • Up to 65K logic cells, 3.3 Mb embedded memory, 128 18 x 18 multipliers, 380 programmable I/O, one lane of 5 Gbps PCIe, two lanes of 1 Gbps GigE, two ADCs (each 12-bit, 1 MSPS).
  • Packages as small as 6x6 mm, and in ball-pitch options of 0.5 and 0.8 mm.
  • Power modes – User selectable Low Power vs. High Performance modes, enabled by FD-SOI programmable back-bias.
  • Design security – ECDSA bitstream authentication, coupled with robust AES-256 encryption.
  • Instant-on configuration – I/O configures in 3 ms, and full-device as fast as 8 ms.
  • Available in Commercial, Industrial and Automotive (AEC-Q100 qualified) temperature grades.

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Certus-NX and CertusPro-NX Device Selection Guide
Certus-NX Device Selection Guide CertusPro-NX Device Selection Guide
Features LFD2NX-9 LFD2NX-15 LFD2NX-17 LFD2NX-25 LFD2NX-28 LFD2NX-35 LFD2NX-40 LFD2NX-65 LFCPNX-50 LFCPNX-100
Logic Cells 9K 15K 17K 25K 28K 35K 39K 65K 52K 96K
Embedded Memory (EBR) Bits (kb) 270 864 432 1440 1044 1890 1512 2304 1728 3744
Large Memory (LRAM) Bits (kb) 1536 512 2560 512 1024 512 1024 1024 2048 3584
18 X 18 Multipliers 12 12 24 20 40 48 56 128 96 156
ADC Blocks 2 2 2 2 2 2 2 2 2 2
GPLL 2 2 2 2 3 2 3 2 3 4
PCIe Hard IP — — — — Gen2 Gen2 Gen2 Gen2 Gen3 Gen3
DDR Memory DDR3/DDR3L, LPDDR2 1066Mbps x 16 DDR3/3L, LPDDR2/LPDDR4 1066Mbps x64
Temperature Grades1 (ms) C, I, A C, I C, I, A C, I C, I, A C, I C, I, A C, I C, I, A C, I, A
0.5 mm Total I/O (Wide Range, High Performance, ADC2) / PCIe Lane
LFD2NX-9 LFD2NX-15 LFD2NX-17 LFD2NX-25 LFD2NX-28 LFD2NX-35 LFD2NX-40 LFD2NX-65 LFCPNX-50 LFCPNX-100
121 csfBGA (6 x 6 mm) 77(23,48,6)/0 — 77(23,48,6)/0 — 81(23,58,0)/1 — 81(23,58 0)/1 — —
256 ASG256 (9 x 9 mm) — — — — — — — — 165(75,84,6)/4 165(75,84,6)/4
0.8 mm Total I/O (Wide Range, High Performance, ADC2) / PCIe Lane

LFD2NX-9 LFD2NX-15 LFD2NX-17 LFD2NX-25 LFD2NX-28 LFD2NX-35 LFD2NX-40 LFD2NX-65 LFCPNX-50 LFCPNX-100
196 caBGA (12 x 12 mm) 77(23,48,6)/0 — 77(23,48,6)/0 — 156(92,58,6)/0 — 156(92,58,6)/0 — — —
256 caBGA (14 x 14 mm) — 205(159,40,6)/0 — 205(159,40,6)/0 191(111,74,6)/1 ​ 181(145,30,6)/1 191(111,74,6)/1 ​ 181(145,30,6)/1 — —
256 CBG256 (14 x 14 mm) — — — — — — — — 165(75,84,6)/4 165(75,84,6)/4
400 caBGA (17 x 17 mm) — 311(257,48,6)/0​ — 311(257,48,6)/0​ — 313(259,48,6)/0 — 313(259,48,6)/0 — —
484 BBG484 (19 x 19 mm) — — — — — 371(317,48,6)/1 — 371(317,48,6)/1 269(167,96,6)/4 305(167,132,6)/8
1.0 mm Total I/O (Wide Range, High Performance, ADC2) / PCIe Lane

LFD2NX-9 LFD2NX-15 LFD2NX-17 LFD2NX-25 LFD2NX-28 LFD2NX-35 LFD2NX-40 LFD2NX-65 LFCPNX-50 LFCPNX-100
484 BFG484 (23 x 23 mm)3 — — — — — — — — 269(167,96,6)/4 305(167,132,6)/4
672 LFG672 (27 x 27 mm)3 — — — — — — — — — 305(167,132,6)/8

1. C = Commercial, I = Industrial, A = Automotive
2. Each ADC pin count reflects using dedicated complement pair and vRef
3. Not available in Automotive Grade

Example Solutions

PCIe to SGMII Bridge Block Diagram with Certus-NXExpand Image

PCIe to GigE Bridge

  • Bridge processor to Ethernet via PCIe Gen2
  • Compact packages as small as 6x6 mm with PCIe and GigE support
  • Hard blocks for PCIe Gen2 eases development
PCIe Control Place Bridge Block Diagram with Certus-NXExpand Image

PCIe Control Plane Bridge

  • Bridge processor via PCIe Gen2 to multiple control plane peripherals (UART, SPI, I2C, MDIO, etc.) and board management functions
  • Packages with high # of programmable I/O per mm2 maximizes # of interfaces in a given form-factor
  • PCIe hard IP with built-in Multi-function support simplifies development
  • Instant-on configuration supports board management needs and PCIe boot-time requirements
Co:processing Block Diagram with Certus-NXExpand Image

Co-processing

  • Off-load CPU by using Certus-NX as a co-processor to accelerate complex functions
  • DDR3 & LPDDR2 interface support (up to 1066 Mbps) and on-chip embedded memory (up to 2.9 Mbit) provide multiple options for data buffering
  • Compact packages as small as 6x6 mm with PCIe and DDR memory interface support
Motor Control Block Diagram with Certus-NXExpand Image

Motor Control

  • Increase efficiency and performance of motor control functions
  • High reliability due to 100x lower Soft Error Rate (SER) from 28 nm FD-SOI technology
  • Industrial temperature support

Video

Certus-NX: Power Consumption Comparison
Expand Video

Certus-NX: Power Consumption Comparison

See a competitive power consumption demo comparing the power consumption of a Lattice Certus-NX running a 5 Gbps PCIe design with two similar competing FPGAs.

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