CrossLink-NX

Embedded Vision and Processing FPGA

Built on the Lattice Nexus Platform - Up to 75% lower power vs similar FPGAs and small form factor packaging with sizes as small as 4 mm x 4 mm.

Provides Best-in-class Performance for Vision Processing Applications - Abundant DSP resources as well as high memory to logic cell ratio (up to 170 bits per logic cell) accelerates AI inferencing.

High Speed Interfaces - 2.5 Gbps Hardened MIPI D-PHY, 5 Gbps PCIe, 5 Gbps USB 3.2, 1.5 Gbps programmable I/O, 1066 Mbps DDR3. Supporting LVDS, subLVDS, OpenLDI (OLDI), and GigE.

Low Power Standby Mode and USB Interface - Consumes < 70 uA of current under typical standby mode.

Features

  • Instant-on configuration – IO configures in 3 ms, and device as fast as 8 ms
  • Up to two hardened 4-lane MIPI D-PHY transceivers at 10 Gbps per PHY / 2.5 Gbps per lane
  • Up to 37 programmable source synchronous I/O pairs for camera and display interfacing
  • From 4 mm x 4 mm WLCS package (0.4 mm pitch) to 17 mm x 17 mm BGA package (0.8 mm pitch)
  • Lowest soft error rate in its class, 100X more reliable than competition
  • Available in Commercial, Industrial and Automotive (AEC-Q100 qualified) temperature grades

Jump to

Family Table

CrossLink-NX Device Selection Guide
Features CrossLink-NX CrossLinkU-NX
Devices LIFCL-17 LIFCL-33 LIFCL-40 LIFCL-33U
Logic Cells 17k 33k 39k 33k
Embedded Memory (EBR) Bits (Kb) 432 1152 1512 1152
Large Memory (LRAM) Bits (Kb) 2560 2560 1024 2560
18 X 18 Multipliers 24 64 56 64
ADC Blocks 2 2
GPLL 2 1 3 1
Hardened 10 Gbps D-PHY Quads 2 2
5 Gb/s PCIe Gen2 Hard IP 1
Temperature Grades 1 C, I, A C, I C, I, A C, I
Always On (AON) Block 1
USB 2.0/USB 3.2 Gen 1 Interface6 1/1
0.4 mm Total I/O (Wide Range, High Performance, ADC3) (D-PHY Quads4, PCIe Lane5)

LIFCL-17 LIFCL-33 LIFCL-40 LIFCL-33U
72 WLCSP (3.7 x 4.1 mm) 39 (15, 24, 0) (1, 0)
0.5 mm Total I/O (Wide Range, High Performance, ADC3) (D-PHY Quads4, PCIe Lane5)

LIFCL-17 LIFCL-33 LIFCL-40 LIFCL-33U
72 QFN (10 x 10 mm) 40 (18, 22, 0) (1, 0) 39 (17, 22, 0) (1, 0)
84 WLCSP (3.1 x 7.4 mm) 60 (34, 26, 0) (0, 0) 44 (17, 27, 0) (0, 0)
121 csfBGA (6 x 6 mm)2 71 (23, 48, 0) (2, 0) 71 (23, 48, 0) (2, 0)
289 csBGA (9.5 x 9.5 mm) 179 (99, 74, 6) (2, 1)
0.65 mm Total I/O (Wide Range, High Performance, ADC3) (D-PHY Quads4, PCIe Lane5)

LIFCL-17 LIFCL-33 LIFCL-40 LIFCL-33U
104 fcCSP (5.5 x 8.5 mm)2 52 (20, 32, 0) (0, 0)
0.8 mm Total I/O (Wide Range, High Performance, ADC3) (D-PHY Quads4, PCIe Lane5)

LIFCL-17 LIFCL-33 LIFCL-40 LIFCL-33U
256 caBGA (14 x 14 mm)2 77 (23, 48, 6) (2, 0) 162 (82, 74, 6) (2, 1)
400 caBGA (17 x 17 mm) 191 (111, 74, 6) (2, 1)

1. C = Commercial, I = Industrial, A = Automotive
2. Package available in Automotive grade
3. Each ADC pin count reflects using dedicated complement pair and vRef
4. Each D-PHY quad consists of 4 D-PHY data lanes
5. Each PCIe lane consists of a Tx and Rx complement pair

Example Solutions

USB to Peripheral Interface Bridging

  • Create plug n play peripheral expansion on USB-enabled FPGA
  • Signal protocol conversion from USB 2.0 to I2C, SPI, and GPIO
  • Signal aggregation and de-aggregation over USB 2.0

Sensor Bridging Over USB

  • Bridge MIPI CSI-2 image sensor to USB interface
  • Signal protocol conversion from MIPI CSI-2 to USB
  • Uncompressed sensor bandwidth up to USB 3.2 Gen 1 (5 Gbps)

Edge AI Processing

  • Bridge one or multiple CSI-2 image sensors to processor interface (PCIe, CMOS, CSI-2)
  • Up to 3 Mb of internal RAM for processing
  • Offloads inferencing from CPU for object detection / counting
  • Combine video bridging and edge AI into a single device

Sensor Aggregation

  • Aggregate up to 11 MIPI CSI-2 image sensors into one MIPI CSI-2 output
  • Stitch data together into larger horizontal video frame
  • Use external DDR memory to stitch data into larger vertical video frame
  • Arbitrate data from image sensors using unique virtual channel numbers
  • Extend limited processor sensor interface capability and connect more sensors

Image Sensor Processing

  • Bridge one or multiple CSI-2 image sensors to processor interface (PCIe, CMOS, CSI-2)
  • Integrate full functional universal video pipeline
  • Examples: Debayer, color correction matrix, RGB gain, gamma correction…
  • Offloads ISP functionality from the processor

Signal Split or Duplication

  • Split or duplicate input CSI-2/DSI signal to multiple video outputs (up to 14)
  • Provide redundancy to sensor data in safety critical applications
  • Simplify applications which require one input to many display outputs

Videos

AIZip Ultra-Efficient Speaker Identification Model on Lattice CrossLink™-NX-33

This demo showcases a robust speaker identification model developed and deployed by Aizip Inc. The efficient neural network-based model can register multiple speakers and provide accurate, low-latency identification results. Co-designed to leverage the superior capabilities of the Lattice CrossLink™-NX-33 board, it features an optimized hardware accelerator to support model computations.

Arrow & Citrobits Cross-Platform Vision AI Workloads Enabled by Lattice CrossLinkU™-NX

The Lattice CrossLinkU™-NX FPGA implements the USB Video Device Class (UVC) standard, allowing you to directly connect a MIPI-based camera module to various application processors, like the NVIDIA Jetson, Qualcomm QCS6490, and NXP i.MX9x. This is made possible by the Citrobits CrossLinkU-NX-based CBM110 USB bridge/aggregator module, which acts as a bridge between the MIPI camera module and the USB interface. The UVC standard simplifies the process of integrating the camera with the host processor.

Helion GmbH Smart Home Video Surveillance

This demo features a smart, low-power home video surveillance system based on the Lattice CrossLink™-NX 40 platform. It delivers 1080p30 video with less than 1.5W power consumption for the entire camera. The ispChain used in this demo will be available for customer use across all Lattice Nexus™ and Lattice Avant™ devices.

Industrial HMI

This demo showcases industrial human-machine interface (HMI) with advanced operated attention sensing and identification. Seamlessly connect with your machinery, gaining real-time insights and control.

Lattice CrosslinkU-NX USB3 Vision (U3V) Reference Design

The USB3 Vision Reference Design with Lattice CrosslinkU-NX device enables video streaming solution from external image sensor to host through MIPI <-> USB3. This solution is in compliance with USB3 Vision standard V1.2 which is widely applicable in Industrial and IOT segment. U3V RD provides methods for camera control, triggering, synchronization through software integration that follows GenICam standard.

Lumotive Beam Steering Chip-Based Lidar

This demonstration showcases Light Surface Metamaterial (LCM) technology for advanced beam steering. Similar to developing a camera module, it features software-defined ROI capabilities for Virtual lidars. This cutting-edge technology offers extended range, higher FPS, and enhanced resolution, all dynamically driven by object detection or perception layers.

SLS MIPI Cameras to USB3 Bridging Using USB Video Class & RAW Data Transfer over USB3

Dual MIPI D-PHY CSI-2 to USB3 Video Class Bridge on Lattice CrossLink™-NX: Seamlessly convert MIPI streams to USB3 with our cutting-edge FPGA design. This solution leverages the OS’s built-in USB Video Class driver, eliminating the need for USB driver development.Real-Time USB3 Throughput Measurement Using Lattice CrossLinkU™-NX: This demonstration accurately assesses data transfer speeds to ensure optimal performance. The Lattice CrossLinkU-NX platform provides a robust and reliable environment for capturing high-speed data.

TinyVision.ai Object Detection/Tracking on CrosslinkU-NX33: StreamLogic

This demonstration showcases Object Detection/Tracking on CrosslinkU-NX33 with StreamLogic, utilizing the TinyVision tinyCLUNX33 SoM and a no-code GUI with RTL generation. Features include an ISP supporting 1920x1080 at 30 fps, advanced image processing, and accelerated object detection based on edge detection.

TinyVision.ai tinyCLUNX33 SoM Lattice CrossLinkU™-NX33

The tinyCLUNX33 SoM featuring the Lattice CrossLinkU-NX33 is a highly integrated, production-friendly System on Module designed for rapid prototyping with a clear path to production.

Introducing CrossLink-NX

CrossLink-NX FPGA is the first family of FPGAs implemented on the new Lattice Nexus Platform. CrossLink-NX provides the energy efficiency, small form factor, high reliability and higher performance developers need to enable innovative embedded vision solutions for the Edge.

CrossLink-NX: Power Efficiency Demo

This demonstration measures the power consumption of Lattice’s CrossLink-NX FPGAs relative to other similar FPGAs using commercially available boards.

CrossLink-NX: Instant On Demo

This demonstration measures the IO wakeup time of Lattice’s CrossLink-NX FPGAs relative to other similar FPGAs using commercially available development boards.

CrossLink-NX: Embedded Vision Demo

This demonstration shows a development board equipped with a CrossLink-NX FPGA, based on the Lattice Nexus platform. The FPGA has been programmed to perform camera aggregation, which is a common embedded vision use case found in many applications.

CrossLink-NX: Human Presence Demo

This demonstration shows a development board equipped with a CrossLink-NX FPGA, based on the Lattice Nexus platform. The FPGA has been programmed to perform human presence detection and counting, which is a common AI use case found in many applications.

Awards

Electroniques 2021 Electrons D'or Awards

Digital IC

Business Intelligence AI Excellence Award

2021 Finalist

The Electronics Industry Awards 2020

Embedded Solution Product of the Year

Leadership in Engineering Achievement Program (LEAP) Awards 2020

Bronze Medal- Embedded Computing Category

2020 Electronics Maker Best of Industry Awards

Best FPGA Award (Technology & Product Innovation category)

Design Resources

Development Kits & Boards

Our development boards & kits help streamline your design process

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Complete Design Flows, High Ease of Use

Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLENUMBERVERSIONDATEFORMATSIZE
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ADC User Guide for Nexus Platform
FPGA-TN-021292.21/6/2026PDF1.3 MB
Advanced Configuration Security Usage Guide for Nexus Platform
FPGA-TN-021761.56/23/2021PDF2.8 MB
Common Programming and Configuration FAQs with Supplementary Concepts for CrossLink-NX, Certus-NX, and CertusPro-NX
FPGA-AN-020481.51/16/2025PDF1.8 MB
CrossLink-NX caBGA256 Pin Migration Table
FPGA-SC-020141.010/27/2020CSV16.5 KB
CrossLink-NX csfBGA121 Pin Migration Table
FPGA-SC-020161.010/27/2020CSV9.2 KB
CrossLink-NX Family Data Sheet
FPGA-DS-020492.36/3/2025PDF4 MB
CrossLink-NX Hardened D-PHY Usage Guide
FPGA-TN-020811.16/21/2021PDF1.2 MB
CrossLink-NX Hardware Checklist
FPGA-TN-021491.712/1/2025PDF857.2 KB
CrossLink-NX High-Speed I/O Interface
FPGA-TN-020972.07/9/2025PDF3.1 MB
CrossLink-NX LIFCL-17 Pinout
FPGA-SC-020060.9210/26/2020CSV10.6 KB
CrossLink-NX LIFCL-33-Pinout
FPGA-SC-020400.808/31/2023CSV3.5 KB
CrossLink-NX LIFCL-33U-Pinout
FPGA-SC-020500.79/26/2023CSV4.3 KB
CrossLink-NX LIFCL-40 Pinout
FPGA-SC-020181.2112/28/2020CSV35.5 KB
CrossLink-NX QFN72 Pin Migration Table
FPGA-SC-020151.15/25/2022CSV5.6 KB
CrossLink-NX-33 and CrossLinkU-NX Data Sheet
FPGA-DS-021041.28/5/2025PDF1.9 MB
CrossLink-NX-33 and CrossLinkU-NX Hardware Checklist
FPGA-TN-023081.410/24/2025PDF901.5 KB
CrossLink-NX-33 and CrossLinkU-NX High-Speed I/O Interface
FPGA-TN-022800.869/3/2025PDF1.3 MB
I2C Hardened IP Usage Guide for Nexus Platform
FPGA-TN-021421.35/31/2022PDF1.4 MB
I3C Controller Driver API Reference
FPGA-TN-023421.012/21/2023PDF894.8 KB
I3C Target Driver API Reference
FPGA-TN-023381.012/21/2023PDF769.7 KB
Lattice Memory Mapped Interface (LMMI) and Lattice Interrupt Interface (LINTR) User Guide
FPGA-UG-020391.25/31/2022PDF1.7 MB
Lattice OrCAD Capture Schematic Library
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
FPGA-SC-020059.012/16/2025ZIP3.2 MB
Memory User Guide for Nexus Platform
FPGA-TN-020941.810/1/2025PDF2 MB
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-021984.612/11/2025PDF1.6 MB
MIPI D-PHY Bandwidth Matrix and Implementation
FPGA-TN-020901.412/11/2025PDF957.3 KB
Multi-Boot User Guide for Nexus Platform
FPGA-TN-021452.48/27/2025PDF1.4 MB
Package Diagrams
FPGA-DS-020538.58/5/2025PDF9.4 MB
PCB Layout Recommendations for BGA Packages
FPGA-TN-020245.612/10/2024PDF6.2 MB
Power Management and Calculation for CrossLink-NX Devices
FPGA-TN-020751.37/15/2021PDF1 MB
Single Event Upset (SEU) Report for Nexus Platform
FPGA-TN-021741.810/13/2025PDF453.7 KB
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-020762.310/13/2025PDF806.2 KB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-020415.212/11/2025PDF533.3 KB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-020282.612/10/2024PDF560.4 KB
sysCLOCK PLL Design and User Guide for Nexus Platform
FPGA-TN-020952.710/13/2025PDF1.9 MB
sysCONFIG User Guide for Nexus Platform
FPGA-TN-020993.57/15/2025PDF4.1 MB
sysDSP User Guide for Nexus Platform
FPGA-TN-020961.76/26/2024PDF1.3 MB
sysI/O User Guide for Nexus Platform
FPGA-TN-020672.810/13/2025PDF820.9 KB
Thermal Management
FPGA-TN-020445.812/11/2025PDF1.1 MB
TransFR Usage Guide for Nexus Platform
FPGA-TN-021731.16/24/2020PDF813.8 KB
Triple-Speed Ethernet Driver API Reference
FPGA-TN-023411.26/26/2025PDF568.1 KB
Using TraceID
FPGA-TN-020842.912/11/2025PDF491.6 KB
Wafer-Level Chip-Scale Package Guide
FPGA-TN-023121.16/23/2022PDF236.5 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

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CrossLink-NX Family Data Sheet
FPGA-DS-020492.36/3/2025PDF4 MB
CrossLink-NX-33 and CrossLinkU-NX Data Sheet
FPGA-DS-021041.28/5/2025PDF1.9 MB
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ADC User Guide for Nexus Platform
FPGA-TN-021292.21/6/2026PDF1.3 MB
Adding Scalable Power and Thermal Management to Nexus FPGAs
FPGA-AN-020791.01/31/2024PDF1.3 MB
Advanced Configuration Security Usage Guide for Nexus Platform
Access this document via a Technical Support Request after signing in to the Lattice website. Complete the request form via this link, please click here.
FPGA-TN-021762.19/23/2025WEB
Advanced Configuration Security Usage Guide for Nexus Platform
FPGA-TN-021761.56/23/2021PDF2.8 MB
Common Programming and Configuration FAQs with Supplementary Concepts for CrossLink-NX, Certus-NX, and CertusPro-NX
FPGA-AN-020481.51/16/2025PDF1.8 MB
CrossLink-NX Hardened D-PHY Usage Guide
FPGA-TN-020811.16/21/2021PDF1.2 MB
CrossLink-NX Hardware Checklist
FPGA-TN-021491.712/1/2025PDF857.2 KB
CrossLink-NX High-Speed I/O Interface
FPGA-TN-020972.07/9/2025PDF3.1 MB
CrossLink-NX-33 and CrossLinkU-NX Hardware Checklist
FPGA-TN-023081.410/24/2025PDF901.5 KB
CrossLink-NX-33 and CrossLinkU-NX High-Speed I/O Interface
FPGA-TN-022800.869/3/2025PDF1.3 MB
CrossLink-NX-33 Image Sensor Module Design Guide
FPGA-AN-020541.06/16/2022PDF396.1 KB
I2C Hardened IP Usage Guide for Nexus Platform
FPGA-TN-021421.35/31/2022PDF1.4 MB
I3C Controller Driver API Reference
FPGA-TN-023421.012/21/2023PDF894.8 KB
I3C Target Driver API Reference
FPGA-TN-023381.012/21/2023PDF769.7 KB
Memory User Guide for Nexus Platform
FPGA-TN-020941.810/1/2025PDF2 MB
Migrating Designs from AMD CPLD/FPGA Devices to Lattice FPGA Devices
FPGA-AN-020811.18/27/2024PDF2.6 MB
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-021984.612/11/2025PDF1.6 MB
MIPI D-PHY Bandwidth Matrix and Implementation
FPGA-TN-020901.412/11/2025PDF957.3 KB
Multi-Boot User Guide for Nexus Platform
FPGA-TN-021452.48/27/2025PDF1.4 MB
PCB Layout Recommendations for BGA Packages
FPGA-TN-020245.612/10/2024PDF6.2 MB
Power Management and Calculation for CrossLink-NX Devices
FPGA-TN-020751.37/15/2021PDF1 MB
Single Event Upset (SEU) Report for Nexus Platform
FPGA-TN-021741.810/13/2025PDF453.7 KB
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-020762.310/13/2025PDF806.2 KB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-020415.212/11/2025PDF533.3 KB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-020282.612/10/2024PDF560.4 KB
sysCLOCK PLL Design and User Guide for Nexus Platform
FPGA-TN-020952.710/13/2025PDF1.9 MB
sysCONFIG User Guide for Nexus Platform
FPGA-TN-020993.57/15/2025PDF4.1 MB
sysDSP User Guide for Nexus Platform
FPGA-TN-020961.76/26/2024PDF1.3 MB
sysI/O User Guide for Nexus Platform
FPGA-TN-020672.810/13/2025PDF820.9 KB
Thermal Management
FPGA-TN-020445.812/11/2025PDF1.1 MB
TransFR Usage Guide for Nexus Platform
FPGA-TN-021731.16/24/2020PDF813.8 KB
Triple-Speed Ethernet Driver API Reference
FPGA-TN-023411.26/26/2025PDF568.1 KB
Using TraceID
FPGA-TN-020842.912/11/2025PDF491.6 KB
Wafer-Level Chip-Scale Package Guide
FPGA-TN-023121.16/23/2022PDF236.5 KB
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CrossLink-NX and Certus-NX Pin Migration
FPGA-TN-022181.03/22/2024PDF495.5 KB
CrossLink-NX caBGA256 Pin Migration Table
FPGA-SC-020141.010/27/2020CSV16.5 KB
CrossLink-NX csfBGA121 Pin Migration Table
FPGA-SC-020161.010/27/2020CSV9.2 KB
CrossLink-NX LIFCL-17 Pinout
FPGA-SC-020060.9210/26/2020CSV10.6 KB
CrossLink-NX LIFCL-33-Pinout
FPGA-SC-020400.808/31/2023CSV3.5 KB
CrossLink-NX LIFCL-33U-Pinout
FPGA-SC-020500.79/26/2023CSV4.3 KB
CrossLink-NX LIFCL-40 Pinout
FPGA-SC-020181.2112/28/2020CSV35.5 KB
CrossLink-NX QFN72 Pin Migration Table
FPGA-SC-020151.15/25/2022CSV5.6 KB
CrossLink-NX-17-Package-DD
1.01/10/2024CSV19 KB
CrossLink-NX-40-BG256-DD
1.010/16/2024CSV29.3 KB
Package Diagrams
FPGA-DS-020538.58/5/2025PDF9.4 MB
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Always ON Module User Guide - Lattice Radiant Software
FPGA-IPUG-022161.09/26/2023PDF554.6 KB
Lattice Memory Mapped Interface (LMMI) and Lattice Interrupt Interface (LINTR) User Guide
FPGA-UG-020391.25/31/2022PDF1.7 MB
sysCLOCK PLL Design and User Guide for Nexus Platform
FPGA-TN-020952.710/13/2025PDF1.9 MB
sysCONFIG User Guide for Nexus Platform
FPGA-TN-020993.57/15/2025PDF4.1 MB
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HyperRAM Memory Controller
FPGA-RD-022361.08/20/2021PDF2.6 MB
subLVDS to MIPI CSI-2 Image Sensor Bridge with CrossLink-NX - Documentation
FPGA-RD-022171.05/1/2021PDF2.5 MB
subLVDS to MIPI CSI-2 Image Sensor Bridge with CrossLink-NX - Source Code
FPGA-RD-022171.05/1/2021ZIP6.2 MB
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Design Advisory for Nexus LVDS-based SGMII
FPGA-DA2506011.06/3/2025PDF77.4 KB
Notification of Changes to CrossLink-NX™ Data Sheet and Certus-NX™ Data Sheet
PCN02A-221.04/4/2022PDF329.6 KB
PCN02A-21- Release of Crosslink‐NX Datasheet Revision 1.2
PCN02A-211.010/19/2021PDF93.7 KB
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Lattice OrCAD Capture Schematic Library
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
FPGA-SC-020059.012/16/2025ZIP3.2 MB
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CrossLink-NX Product Brochure
I02692.03/31/2021PDF441.3 KB
Lattice FPGA Product Selector Guide
v25.3.01/6/2026PDF717 KB
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Lattice Crosslink-NX: Embedded Vision Processing at the Edge
1.01/18/2020PDF523.2 KB
Random Bin Picking Based On Structured-Light 3D Scanning
WP00432.05/22/2025PDF3.7 MB
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[BSDL] LIFCL-17
FPGA-MD-020101.1412/16/2019ZIP19.2 KB
[BSDL] LIFCL-33 BBG484
FPGA-MD-020291.156/7/2022BSM32 KB
[BSDL] LIFCL-33 WLCSP84
FPGA-MD-020301.156/7/2022BSM20.6 KB
[BSDL] LIFCL-33U FCCSP104
FPGA-MD-020511.149/26/2023BSM20.4 KB
[BSDL] LIFCL-33U WLCSP84
FPGA-MD-020501.149/26/2023BSM18.9 KB
[BSDL] LIFCL-40
FPGA-MD-020611.04/15/2024ZIP35.3 KB
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CrossLink-NX Device Family DELPHI Models
FPGA-MD-020321.012/10/2019ZIP191.5 KB
CrossLinkU-NX DELPHI Models
FPGA-MD-020540.8110/19/2023ZIP22.7 KB
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[IBIS] LIFCL-17 and LIFCL-40
FPGA-MD-020671.06/27/2024ZIP12.6 MB
[IBIS] LIFCL-33 and LIFCL-33U
FPGA-MD-020361.26/27/2024ZIP12.5 MB

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