iCE40 UltraPlus

ML/AI Low Power FPGA

Low Power Connectivity and Computing – With the rising complexity of systems used to power smart homes, factories and cities, the iCE40 UltraPlus FPGA can solve connectivity issues with a wide variety of interfaces and protocols and provide the low power computational resources for higher levels of intelligence.

Edge Intelligent FPGA – The iCE40 UltraPlus FPGA with 5k lookup tables (LUTs) is able to implement Neural Networks for pattern matching necessary to bring always-on intelligence to the edge. Optimized for best-in-class power, designers can eliminate latency associated with cloud intelligence while keeping the overall system solution cost low.

Flexible Package Options – Multiple package are available to fit a wide range of applications needs. From an ultra-small 2.15 x 2.50 mm WLCSP package optimized for consumer and IoT devices, to a 0.5 mm pitch 7 x 7 mm QFN for cost optimized applications.

Features

  • Flexible logic architecture with 2800 or 5280 4 input LUTs, customizable I/O, up to 80 kbits of embedded dual port memory and 1 Mbit of embedded single port memory
  • Ultra-low power advanced process with static current as low as 75 uA and 1-10 mA active current for most applications
  • High performance signal processing using DSP blocks with multiply and accumulate functions
  • Soft Neural Network IPs and compiler for flexible Machine Learning/AI implementation
  • FPGA design tools, demos and reference designs to kick start designs
ACE 2017 Finalist Award 

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iCE40 UltraPLus Device Selection Guide
Parameter UP3K UP5K
Density LUTs 2800 5280
NVCM Yes Yes
Static Current (uA)
75 75
EBR RAM (kbits) 80 120
SPRAM (kbits) 1024 1024
PLL 1 1
I2C Core 2 2
SPI Core 2 2
Oscillator (10 kHz) 1 1
Oscillator (48 MHz) 1 1
24 mA Drive 3 3
500 mA Drive - -
16 x 16 Multiply & 32 bit Accumulator Blocks 4 8
PWM Yes Yes
0.4 mm Spacing Total I/O + Dedicated Inputs1,2
  UP3K UP5K
30-ball WLCSP (2.15 x 2.55 mm) 21 21
0.5 mm Spacing Total I/O + Dedicated Inputs1,2
  UP3K UP5K
48-pin QFN (7 x 7 mm) - 39

1. Total I/O include Dedicated I/O
2. Dedicated I/O are defined to be pins that are dedicated and cannot be used by user logic after configuration

Example Solutions

Binarized Neural Network (BNN) Accelerator IP

  • Take advantage of the FPGA’s parallel processing capability to implement machine learning algorithms.
  • Enables implementation of BNNs that have power consumption in the mW range.

Key Phrase Detection – Lattice SensAI

  • Enable systems to always search for key phrases using a digital microphone input.
  • Consumes less than 1 mW of average power.

Human Face Detection

  • Enable artificial intelligence with an always-on image sensor, while consuming less than 1 mW of active power.
  • Frame rate and power consumption adjustable to meet system power requirements.

Single Wire aggregation

  • Aggregate multiple interfaces over one single data wire.
  • Single wire speed of up to 7.5 Mbps.
  • Robust protocol with error detection and retry features.

8:1 Microphone Aggregation

  • Aggregate 8 PDM microphones and connection to a processor over I2S or SPI.
  • Enables use of multiple microphone for beam forming in smart speakers.

Design Resources

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Development Kits & Boards

Our development boards & kits help streamline your design process

Complete Design Flows, High Ease of Use

Programming Hardware

Take the strain out of in-system programming & in-circuit reconfiguration with our programming hardware

Videos

Introducing iCE40 UltraPlus

Lattice expands its mobile FPGA product family with the iCE40 UltraPlus, delivering eight times more memory (1.1 Mbit RAM), twice the digital signal processor blocks (8x DSPs), and improved I/O over previous generations. In this video, learn more about iCE40 UltraPlus capabilities, such as driving a MIPI DSI display along with integrated SRAM memory for frame buffering.

Human Face Detection Demo

Learn how iCE40 UltraPlus can help you with the implementation of human face detection using a neural network.

Awards

China Electronic Market 2016 Editor's Choice Awards

Most Competitive FPGA Product

Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLENUMBERVERSIONDATEFORMATSIZE
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Advanced iCE40 I2C and SPI Hardened IP User Guide
FPGA-TN-020111.87/29/2025PDF1.6 MB
DSP Function Usage Guide for ICE40 Devices
FPGA-TN-020071.212/15/2020PDF947.4 KB
iCE40 Hardware Checklist
FPGA-TN-020062.410/24/2025PDF712.4 KB
iCE40 I2C and SPI Hardened IP - Usage Guide
FPGA-TN-020101.811/1/2022PDF952 KB
iCE40 LED Driver User Guide
FPGA-TN-020211.511/29/2021PDF2 MB
iCE40 Oscillator User Guide
FPGA-TN-020081.84/12/2023PDF443.1 KB
iCE40 Programming and Configuration
FPGA-TN-020013.412/31/2022PDF1.8 MB
iCE40 SPRAM Usage Guide
FPGA-TN-020221.43/30/2025PDF395 KB
iCE40 sysCLOCK PLL Design and User Guide
FPGA-TN-020521.44/30/2022PDF1.3 MB
iCE40 Technology Library
FPGA-TN-020263.39/22/2024PDF2.7 MB
iCE40 Ultra & UltraPlus SG48 Pin Migration
2.010/20/2020XLSX15.3 KB
iCE40 UltraPlus Family Data Sheet
FPGA-DS-020082.43/6/2025PDF1.5 MB
iCE40UP WLCSP30 Pin Migration
1.13/16/2018XLSX16.4 KB
iCE40UP3K Pinout
1.13/16/2018XLSX16.1 KB
iCE40UP5K Pinout
1.17/8/2017XLSX15.6 KB
Lattice OrCAD Capture Schematic Library
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
FPGA-SC-020059.012/16/2025ZIP3.2 MB
Memory Usage Guide for iCE40 Devices
FPGA-TN-020021.710/14/2020PDF954.3 KB
Package Diagrams
FPGA-DS-020538.58/5/2025PDF9.4 MB
PCB Layout Recommendations for BGA Packages
FPGA-TN-020245.612/10/2024PDF6.2 MB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-020415.212/11/2025PDF533.3 KB
Thermal Management
FPGA-TN-020445.812/11/2025PDF1.1 MB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

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iCE40 UltraPlus Family Data Sheet
FPGA-DS-020082.43/6/2025PDF1.5 MB
TITLENUMBERVERSIONDATEFORMATSIZE
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Advanced iCE40 I2C and SPI Hardened IP User Guide
FPGA-TN-020111.87/29/2025PDF1.6 MB
DSP Function Usage Guide for ICE40 Devices
FPGA-TN-020071.212/15/2020PDF947.4 KB
iCE40 Hardware Checklist
FPGA-TN-020062.410/24/2025PDF712.4 KB
iCE40 I2C and SPI Hardened IP - Usage Guide
FPGA-TN-020101.811/1/2022PDF952 KB
iCE40 LED Driver User Guide
FPGA-TN-020211.511/29/2021PDF2 MB
iCE40 Oscillator User Guide
FPGA-TN-020081.84/12/2023PDF443.1 KB
iCE40 Programming and Configuration
FPGA-TN-020013.412/31/2022PDF1.8 MB
iCE40 SPRAM Usage Guide
FPGA-TN-020221.43/30/2025PDF395 KB
iCE40 sysCLOCK PLL Design and User Guide
FPGA-TN-020521.44/30/2022PDF1.3 MB
Memory Usage Guide for iCE40 Devices
FPGA-TN-020021.710/14/2020PDF954.3 KB
Migrating Designs from AMD CPLD/FPGA Devices to Lattice FPGA Devices
FPGA-AN-020811.18/27/2024PDF2.6 MB
PCB Layout Recommendations for BGA Packages
FPGA-TN-020245.612/10/2024PDF6.2 MB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-020415.212/11/2025PDF533.3 KB
Thermal Management
FPGA-TN-020445.812/11/2025PDF1.1 MB
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iCE40 Ultra & UltraPlus SG48 Pin Migration
2.010/20/2020XLSX15.3 KB
iCE40UP WLCSP30 Pin Migration
1.13/16/2018XLSX16.4 KB
iCE40UP3K Pinout
1.13/16/2018XLSX16.1 KB
iCE40UP5K Pinout
1.17/8/2017XLSX15.6 KB
Package Diagrams
FPGA-DS-020538.58/5/2025PDF9.4 MB
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iCE40 Technology Library
FPGA-TN-020263.39/22/2024PDF2.7 MB
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iCE40 Ultra Barcode Emulation Design Files
UG731.07/15/2014ZIP5.9 MB
iCE40 Ultra Barcode Emulation User’s Guide
UG731.07/15/2014PDF4.3 MB
iCE40 Ultra RGB LED Controller Design Files
1.07/15/2014ZIP9.2 MB
iCE40 Ultra RGB LED Controller User Guide
UG751.07/15/2014PDF2.9 MB
iCE40 Ultra Self-Learning IR Remote Design Files
UG741.07/15/2014ZIP5.8 MB
iCE40 Ultra Self-Learning IR Remote User’s Guide
UG741.07/15/2014PDF2.9 MB
Sensor Interface and Preprocessing Reference Design - Documentation
FPGA-RD-020481.39/26/2018PDF1.4 MB
Sensor Interfacing and Preprocessing Reference Design - Source Code
1.39/26/2018ZIP1.4 MB
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PCN09A-19 BOM comparison final
2.01/8/2020XLSX24.8 KB
PCN12A-16 KYEC Alternate Qualified Test Site
Test Site
PCN12A-161.08/25/2016PDF184.7 KB
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Lattice OrCAD Capture Schematic Library
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
FPGA-SC-020059.012/16/2025ZIP3.2 MB
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iCE40 UltraPlus Product Brochure
I02553.04/9/2019PDF960.4 KB
Lattice FPGA Product Selector Guide
v25.3.01/6/2026PDF717 KB
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iCE40 FPGA Product Family Qualification Summary
Rev U3/25/2021PDF1 MB
SN_SG48
Rev C19/20/2019PDF52.9 KB
UWG30
Rev B4/19/2018PDF22.7 KB
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IoT Sensor Connectivity and Processing with Ultra-Low Power, Small Form-Factor FPGAs
1.04/3/2018PDF3 MB
The Industry Case for Distributed Heterogeneous Processing
WP00081.012/12/2016PDF641.9 KB
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iCE40 UltraPlus IBIS Model
2.01/16/2018IBS939.6 KB

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