Lattice Propel Design Environment

Build FPGA-based Processor Systems in Minutes

Design Environment for Lattice FPGA-based Processor System Design - Lattice Propel is a complete set of graphical and command-line tools to create, analyze, compile, and debug both the hardware design of an FPGA-based processor system, and the software design for that processor system.

Lattice Propel Builder - An easy to use system IP integration environment, Propel Builder provides tools to integrate processors and peripheral IP. The graphical integration environment features an easy-to-use, drag and drop correct-by-construction methodology. All commands are Tcl scriptable.

Lattice Propel SDK - A seamless software development environment, Propel SDK is a software development kit (SDK) with an integrated industry standard IDE and toolchain. The SDK features SW/HW debugging capabilities along with software libraries and board support packages (BSP) for Propel Builder defined systems.

Features

  • Drag and drop IP instantiation
  • Correct by construction design methodology
  • High productivity HW/SW debugging
  • Software libraries and BSP support
  • Tcl scripting commands
  • Functional Safety Certified. Visit this page for the full list of certified software

Getting Started

  1. Download: Choose and download software from the Software Downloads & Documentation table below
  2. Install: Follow the installation guide, found in Software Downloads & Documentation section below.
  3. License: You will need a Lattice Propel license, Click the button below to request a license.

Jump to

Block Diagrams

Lattice Propel Design Environment
Lattice Propel Design Environment

DesignFlow

Lattice Propel Design Flow
Lattice Propel Builder Design Flow

Lattice Propel Solutions

RISC-V MC CPU IP Core Block Diagram

IP Core

RISC-V MC CPU IP Core

The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).
RISC-V MC CPU IP Core
RISC-V SM CPU IP Core Block Diagram

IP Core

RISC-V SM CPU IP Core

Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
RISC-V SM CPU IP Core
RISC-V RX CPU IP Core_BD

IP Core

RISC-V RX CPU IP Core

Lattice RISC-V RX IP processes data and instructions while monitoring the external interrupts, using 32-bit RISC-V processor core and several submodules.
RISC-V RX CPU IP Core
RISC-V Nano

IP Core

RISC-V Nano CPU IP Core

The RISC-V Nano CPU IP contains a 32-bit RISC-V processor core that supports the RV32I instruction set and a lightweight interrupt merge controller.
RISC-V Nano CPU IP Core
Tightly-Coupled Memory (TCM) IP Core Block Diagram

IP Core

Tightly-Coupled Memory (TCM) IP Core

The Tightly-Coupled Memory (TCM) IP ensures low-latency automatic selection of the best memory type for user-selected application.
Tightly-Coupled Memory (TCM) IP Core

Award

Leadership in Engineering Achievement Program (LEAP) Awards 2020

Gold Medal- Software Category

Software Downloads & Documentation

To subscribe, or modify your subscription, to Document Notifications please login to your Lattice account

Quick Reference
Information Resources
Downloads
TITLENUMBERVERSIONDATEFORMATSIZE
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Lattice IP Packager 2026.1 User Guide
FPGA-UG-022531.06/26/2026
Lattice Propel 2026.1 Builder User Guide
FPGA-UG-022541.06/26/2026
Lattice Propel 2026.1 Installation for Linux User Guide
FPGA-AN-021161.06/26/2026
Lattice Propel 2026.1 Installation for Windows User Guide
FPGA-AN-021171.06/26/2026
Lattice Propel 2026.1 Release Notes
FPGA-AN-021151.06/26/2026PDF451.6 KB
Lattice Propel 2026.1 SDK User Guide
FPGA-UG-022551.06/26/2026
Revision Control – Lattice Propel Builder 2026.1 User Guide
FPGA-UG-022521.06/26/2026
TITLENUMBERVERSIONDATEFORMATSIZE
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Composable Custom Extensions on Lattice RISC-V RX User Guide
FPGA-AN-020751.13/15/2024PDF1.1 MB
Lattice Propel 1.0 API Reference
FPGA-AN-020271.06/3/2020PDF914.5 KB
Lattice Propel 2026.1 Installation for Linux User Guide
FPGA-AN-021161.06/26/2026
Lattice Propel 2026.1 Installation for Windows User Guide
FPGA-AN-021171.06/26/2026
Lattice RISC-V Embedded Design Guidelines
FPGA-AN-020721.13/10/2026PDF3.2 MB
QuestaSim Lattice Edition Usage Guidelines and Tips
FPGA-AN-020531.12/5/2025PDF1.7 MB
Scripting Lattice FPGA Build Flow
FPGA-AN-020731.010/31/2023PDF1.2 MB
TITLENUMBERVERSIONDATEFORMATSIZE
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Lattice Propel 2026.1 Installation for Linux User Guide
FPGA-AN-021161.06/26/2026
Lattice Propel 2026.1 Installation for Windows User Guide
FPGA-AN-021171.06/26/2026
TITLENUMBERVERSIONDATEFORMATSIZE
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Lattice IP Packager 2026.1 User Guide
FPGA-UG-022531.06/26/2026
Lattice Propel 2026.1 Builder User Guide
FPGA-UG-022541.06/26/2026
Lattice Propel 2026.1 SDK User Guide
FPGA-UG-022551.06/26/2026
MachXO5-NX RoT Propel Builder Template to Radiant Project, Security Configuration, and Bitstream Generation
Access this document via a Technical Support Request after signing in to the Lattice website. Complete the request form via this link, please click here.
FPGA-UG-022570.806/16/2026WEB
Revision Control – Lattice Propel Builder 2026.1 User Guide
FPGA-UG-022521.06/26/2026
TITLENUMBERVERSIONDATEFORMATSIZE
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Lattice Propel Product Brochure
IO2722.09/29/2022PDF1.8 MB
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Lattice Propel 2026.1 Release Notes
FPGA-AN-021151.06/26/2026PDF451.6 KB
TITLENUMBERVERSIONDATEFORMATSIZE
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A Step-By-Step Approach to Lattice Propel
FPGA-AN-020521.12/19/2024ZIP6.6 MB
Creating Custom IP with IP Packager
FPGA-AN-021021.04/30/2025ZIP1.8 MB
TITLENUMBERVERSIONDATEFORMATSIZE
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Lattice Propel Helps Designers Create Processor-Based Systems in Minutes
WP00291.02/23/2021PDF503.9 KB
TITLENUMBERVERSIONDATEFORMATSIZE
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Lattice Propel 2026.1 64-bit for Linux
2026.16/26/2026ZIP3.7 GB
Lattice Propel 2026.1 64-bit for Windows
2026.16/26/2026ZIP1.6 GB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

To download old versions of Propel, please visit the Software Archive page.

Propel IP Modules Documentation

To view the full list of documents related to Propel IP Modules, please visit the Lattice IP Modules page.

Licensing

Currently, Lattice Propel Design Environment only requires a Free License.

Notice: If you are upgrading to Propel 2022.1 or later and generated your free Propel license prior to December 2022, please generate a new license to enable proper usage of all tools included in Propel.

Device Support

Device Support by License
Product Subscription License Free License
Avant-E No Check Mark
Avant-G No Check Mark
Avant-X No Check Mark
Certus-N2 No Check Mark
CertusPro-NX No Check Mark
Certus-NX No Check Mark
CrossLink-NX No Check Mark
Mach-NX No Check Mark
MachXO4 No Check Mark
MachXO5-NX No Check Mark
MachXO3D No Check Mark
MachXO3LF No Check Mark
MachXO3L No Check Mark
MachXO2 No Check Mark
iCE40 UltraPlus No Check Mark
ECP5U No Check Mark
ECP5UM No Check Mark
ECP5UM5G No Check Mark
LatticeECP3 No Check Mark
Operating System
Windows
Windows 10
Windows 11
Linux
RHEL 8.10
RHEL 9.6
Ubuntu 22.04 LTS
Ubuntu 24.04 LTS
 
Request License

Propel Feature List

  • Propel Builder – Graphical driven IP integration and system building tool drag and drop instantiation and wizard guided configuration and parameterization.
  • Propel SDK – Software development kit with Industry-standard IDE and toolchain with integrated Gnu Debugging (GDB).
  • Templates for Hello World project
  • System-level functional verification environment for templates

Version History

Click here to see all Propel Version History.

Videos

What’s New in Propel 2026.1

Discover what’s new in Lattice Propel 2026.1, featuring enhancements that improve user experience and streamline intuitive design creation. Watch now to see how the latest updates help you build FPGA-based embedded systems faster and focus on innovation.

Date: June 26, 2026 (English) Watch Now

What’s New in Lattice Propel 2025.2

Lattice Propel 2025.2 focuses on ease of use, improved design creation and accelerated project startup.

Get Started Quickly with Lattice Propel

Lattice Propel is the Embedded Design Environment to implement RISC-V soft processor systems in Lattice FPGAs. This demonstration will guide you through building an embedded design, developing the software for the processor, implementation in the FPGA, and debugging the system all with in the Propel environment.

Propel Simplifies Mach-NX Design

Use Lattice Propel software to add advanced security to a system control FPGA design quickly