CrossLinkProductDetailPagecd1fa365-43d2-47c2-b000-718c990a59c27506888b-123b-4046-8aab-760100c72420Webpage/Products/FPGAandCPLD/CrossLink/Products/FPGAandCPLD/CrossLinkCrossLink combines hardened high-speed video interfaces, flexible high-speed IO, and IP for low power video bridgingapplications supporting LVDS, SLVS, SubLVDS, OpenLDI and RGB interfaces.CrossLink combines hardened high-speed video interfaces, flexible high-speed IO, and IP for low power video bridgingapplications supporting LVDS, SLVS, SubLVDS, OpenLDI and RGB interfaces.Lattice CrossLink low power FPGA featuring hardened MIPI D-PHY, LVDS, SLVS, subLVDS, & Open LDI bridging.Low power FPGA featuring hardened MIPI D-PHY, LVDS, SLVS, subLVDS, & Open LDI bridgingSmall Footprint, Big Features - Do you need to bridge, aggregate, or split signals for cameras and displays? CrossLink is the most versatile device and has a footprint as small as 6 mm 2 . How Low Can We Go - Up to 50% lower power than competition. < 100 mW for many use cases and the first programmable bridging solution with a built-in sleep mode. Sets the Bar in Performance - Industry s fastest MIPI D-PHY bridging solution supporting 4K UHD resolution at speeds up to 12 Gbps. Also supports LVDS, SLVS, subLVDS, and OpenLDI (OLDI). jQuery(document).ready(function() { jQuery('.docTypes').find("a").each(function () { jQuery(this).on('click', function() { ga('send', 'event', 'CrossLink Document Category', 'click', jQuery(this).text()); }); }); jQuery('.jsModalWindow').each(function () { jQuery(this).on('click', function() { ga('send', 'event', 'CrossLink Solutions', 'click', jQuery(this).children("img").attr("alt")); }); }); jQuery('.docList').find("input[type=submit]").each(function () { jQuery(this).on('click', function() { ga('send', 'event', 'CrossLink Zip Download', 'click', 'download as zip'); }); }); jQuery('.sidebarNavBlock').find("img").each(function () { jQuery(this).parent("a").on('click', function() { ga('send', 'event', 'CrossLink Banner', 'click', jQuery(this).children("img").attr("alt")); }); }); jQuery('.video-js').on('click', function() { ga('send', 'event', 'CrossLink Video', 'click', 'start here'); }); jQuery('.action-links').find('href').each(function() { jQuery(this).on('click', function() { ga('send', 'event', 'CrossLink LP Links', 'click', $jQuery(this).text()); }) }); jQuery('video').attr("preload","auto"); jQuery('video').bind("play",function() { Munchkin.munchkinFunction('visitWebPage', { url: '/CrossLink_video_play', params: '' } ); }); });Lattice CrossLink, Low Power FPGA for Video Bridging, Video Bridging FPGA, Lattice FPGA Video Bridging
Small Footprint, Big Features – Do you need to bridge, aggregate, or split signals for cameras and displays? CrossLink is the most versatile device and has a footprint as small as 6 mm2.
How Low Can We Go – Up to 50% lower power than competition. < 100 mW for many use cases and the first programmable bridging solution with a built-in sleep mode.
Sets the Bar in Performance – Industry’s fastest MIPI D-PHY bridging solution supporting 4K UHD resolution at speeds up to 12 Gbps. Also supports LVDS, SLVS, subLVDS, and OpenLDI (OLDI).
Features
- Two 4-lane MIPI D-PHY transceivers at 6 Gbps per PHY
- 15 programmable source synchronous I/O pairs for camera and display interfacing
- Available in amazingly small 2.46 mm x 2.46 mm WLCSP packages and BGA packages with 0.4 mm, 0.5 mm and 0.65 mm pitch
- Flexible device configuration with OTP non-volatile configuration memory and I2C/SPI programming
- More than 5900 LUTs with up to 81 I/O pins
- Soft IP available for multiple bridging solutions here
CrossLink Device Selection Guide
| Features |
LIF-MD6000-36 |
LIF-MD6000-64 |
LIF-MD6000-81 |
LIA-MD6000-81 |
LIF-MD6000-80 |
LIA-MD6000-80 |
LIF-MD6000-80 |
LIA-MD6000-80 |
| LUTs |
5936 |
5936 |
5936 |
5936 |
5936 |
5936 |
5936 |
5936 |
| Embedded Memory (kbits) |
180 |
180 |
180 |
180 |
180 |
180 |
180 |
180 |
| Distributed RAM (kbits) |
47 |
47 |
47 |
47 |
47 |
47 |
47 |
47 |
| GPLL |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| D-PHY PLL |
1 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
| Embedded I2C Blocks |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
| Embedded RX/TX MIPI D-PHY |
1 (4 Data + 1 Clock) |
2 (8 Data + 2 Clock) |
2 (8 Data + 2 Clock) |
2 (8 Data + 2 Clock) |
2 (8 Data + 2 Clock) |
2 (8 Data + 2 Clock) |
2 (8 Data + 2 Clock) |
2 (8 Data + 2 Clock) |
| 48 MHz Oscillator |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| 10 KHz Oscillator |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| NVCM |
Yes |
Yes |
Yes |
Yes |
Yes |
Yes |
Yes |
Yes |
| Dual Boot1 |
Yes |
Yes |
Yes |
Yes |
Yes |
Yes |
Yes |
Yes |
| Power Management Unit |
Yes |
Yes |
Yes |
Yes |
Yes |
Yes |
Yes |
Yes |
| Low Power Sleep Mode |
Yes |
Yes |
Yes |
Yes |
Yes |
Yes |
Yes |
Yes |
| Typical Operational Power |
5 mW - 135 mW |
5 mW - 135 mW |
5 mW - 135 mW |
5 mW - 135 mW |
5 mW - 135 mW |
5 mW - 135 mW |
5 mW - 135 mW |
5 mW - 135 mW |
| Footprint |
2.5 mm x 2.5 mm |
3.5 mm x 3.5 mm |
4.5 mm x 4.5 mm |
4.5 mm x 4.5 mm |
6.5 mm x 6.5 mm |
6.5 mm x 6.5 mm |
7.0 mm x 7.0 mm |
7.0 mm x 7.0 mm |
| Package Pitch |
0.4 mm |
0.4 mm |
0.5 mm |
0.5 mm |
0.65 mm |
0.65 mm |
0.65 mm |
0.65 mm |
| Programmable I/O |
17 |
29 |
37 |
37 |
37 |
37 |
37 |
37 |
| Automotive |
No |
No |
No |
Yes |
No |
Yes |
No |
Yes |
ADAS Application
- Bridge multiple CSI-2 image sensors into one single MIPI CSI-2 output for 360 degree camera application.
- Camera input support from a variety of interfaces like CSI-2, LVDS, Sub-LVDS and LVCMOS.
- Multiple camera interfaces supported to bridge to the Application Processor.
- Stitch data together into larger horizontal video frame.
Multi CSI-2 Image Sensor Interface Bridging Solutions
- Bridge multiple CSI-2 image sensors into one MIPI CSI-2 output
- Configure multiple image sensors with same I2C slave address from one I2C master
- Trigger and synchronize image sensors with GPIO control
- Stitch data together into larger horizontal video frame
- Arbitrate data from image sensors and append unique virtual channel numbers
Click here for more information
Multi MIPI DSI Display Bridging
- Drive multiple MIPI DSI displays or display requiring two MIPI DSI interfaces
- Replicate video to both displays or reduce the bandwidth by half on output over two PHYs
- Control peripheral functions and power sequencing of displays with additional GPIO
Click here for more information
Display Interface Conversion Bridging
- Convert to/from MIPI DSI, OpenLDI/LVDS, and RGB/CMOS
- Support all data types and number of lanes
- Support additional functions such as display and peripheral initialization, control and sequencing
- Crop & scale video data to match special formatting needs
Click here for more information
Camera Interface Conversion Bridging
- Convert to/from MIPI CSI-2, SubLVDS, LVDS, CMOS, HiSPi and other image sensor interfaces
- Control frame and line readout controls for slave driven image sensors
- Convert I2C to SPI for image sensor and peripheral control
- Crop & scale video data to match special formatting needs
Click here for more information
Introduction to CrossLink
Learn how CrossLink can solve interfacing problems including implementing multi CSI-2 bridges for mixing, merging, arbitrating, converting multiple image sensor interfaces to a single applications processor.
CrossLink IP Cores for Mobile Influenced Markets
Check out how CrossLink's collection of IP cores helps you solve design challenges with MIPI interface adoption.
Using Lattice CrossLink FPGA for 360 Surround View Applications
Taking a simple camera and converting it regular image into a 360 surround view doesn't have to be difficult. Learn how our CrossLink FPGA can help.
Adding CrossLink IP Using Clarity Designer
Check out how easy it is to add CrossLink IPs to your designs.
Debug Your Project with Reveal
This video shows you how to add Reveal to debug a project.
Embedded World Awards 2017
Hardware Product Nominee
EEPW Magazine (China) 2016 Editor's Choice Award
Best FPGA Product
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