Platform Manager 2 & L-ASC10

Manage power, thermal & control planes in real time

Reduced time to market – Fast and reliable fault detection/logging for power & thermal management and board control logic, coupled with simulation and in-system debug support.

Simple, scalable, end-to-end – Scalable platform for voltage, temperature, logic and I/O that can be easily expanded using L-ASC10 chips with glue-less interfaces.

Reduce BOM and cost – Designs across a wide range of systems can standardize on the Platform Manager 2 family instead of multiple single function ICs from multiple vendors.

Features

  • Full fault coverage – monitor all rails and temperature nodes
  • Manage from 10 to 80 supplies using just the required number of L-ASC10 hardware management expanders
  • Minimize fault propagation by enabling individual hardware management sub-blocks (power, thermal & control path) to respond to faults in other blocks within nano-seconds
  • Save CPLD I/O pins by eliminating the need to monitor power-good signals of DC-DC converters
  • Reliable power & thermal fault detection in hardware, as opposed to software routines

Jump to

Family Table

Platform Manager 2 Family

Parameters L-ASC10 LPTM21 LPTM21L
Voltage Monitoring Inputs 10 10 10
Current Monitoring Inputs 2 2 2
Temperature Monitoring Inputs 2 2 2
Number of Trimming Channels 4 4 4
MOSFET Drivers 4 4 4
Open Drain GPIO (5 V Tolerant) 9 10 10
On-Chip Non-Volatile Fault Log Check Mark Check Mark Check Mark
Number of LUTs - 1280 1280
Digital I/O Count (PIO) - 98 33
Primary Clock Inputs (PCLK) - 6 4
Distributed RAM (kBits) - 10 10
EBR SRAM (kBits) - 64 64
Number of EBR Blocks (9 kBits) - 7 7
User Flash Memory (kBits) - 64 64
Number of PLLs - 1 1
Communication I/F I2C I2C / JTAG I2C / JTAG
Programming Interface I2C I2C / JTAG I2C / JTAG
Operating Voltage 3.3 V 2.8 V to 12 V 3.3 V
Insystem Update Support Check Mark Check Mark Check Mark
Analog / Digital I/Os
Package Options L-ASC10 LPTM21 LPTM21L
48-pin QFN (7 X 7 mm2) 22 / 9 - -
100-Ball caBGA (10 X 10 mm2) - - 22 / 43
237-Ball ftBGA (17 X 17 mm2) - 22 / 108 -

Example Solutions

Highly Scalable Hardware Management

  • Cut and paste solutions across a wide range of applications, and customize algorithms
  • Simplified board debug through an extensive suite of debug tools
  • Increased reliability with full fault coverage
  • Effortless integration of wide range of functions, such as temperature sense ICs, ADCs, reset generators, current sense ICs, and many digital buffers and controllers

Design Resources

Development Kits & Boards

Our development boards & kits help streamline your design process

Programming Hardware

Take the strain out of in-system programming & in-circuit reconfiguration with our programming hardware

Application Notes

Learn how to get the most from our line-up of FPGAs / development boards

Complete Design Flows, High Ease of Use

Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
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Adding Scalable Power and Thermal Management to ECP5 Using L-ASC10
FPGA-AN-020191.28/7/2023PDF2 MB
Adding Scalable Power and Thermal Management to MachXO2 and MachXO3 Using L-ASC10
FPGA-AN-020111.210/11/2019PDF2.1 MB
Dual Boot and Background Programming with PlatformManager 2
FPGA-TN-020781.310/10/2019PDF1.9 MB
Extending the VMON Input Range of Power/Platform Management Devices
FPGA-AN-020312.59/21/2021PDF1.1 MB
Fault Logging Using Platform Manager 2
TN12772.11/5/2018PDF3.5 MB
Implementing VID Function with Platform Manager 2
AN60921.29/8/2017PDF2.9 MB
Importing HDL Files With Platform Manager 2
TN12871.08/1/2014PDF546.9 KB
Interfacing the Trim Output of Power Manager II Devices to DC-DC Converters
AN60741.24/7/2015PDF3.1 MB
L-ASC10 and Platform Manager 2 Hardware Checklist
FPGA-TN-021751.21/27/2020PDF1.1 MB
L-ASC10 Data Sheet
FPGA-DS-020382.611/28/2024PDF7.8 MB
Lattice OrCAD Capture Schematic Library
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
FPGA-SC-020059.012/16/2025ZIP3.2 MB
Package Diagrams
FPGA-DS-020538.58/5/2025PDF9.4 MB
Platform Manager 2 Data Sheet
FPGA-DS-020362.510/20/2023PDF2.8 MB
Platform Manager 2 PM Bus Adapter Usage
TN12971.02/11/2015PDF2.1 MB
Powering Up and Programming Platform Manager 2 and L-ASC10
AN60912.13/31/2015PDF2 MB
Temperature Monitoring and Fan Control with Platform Manager 2
FPGA-TN-020801.29/30/2018PDF2.6 MB
Using Power MOSFETs with Power/Platform Management Devices
AN60481.38/29/2017PDF734.6 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

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L-ASC10 Data Sheet
FPGA-DS-020382.611/28/2024PDF7.8 MB
Platform Manager 2 Data Sheet
FPGA-DS-020362.510/20/2023PDF2.8 MB
TITLENUMBERVERSIONDATEFORMATSIZE
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Adding Scalable Power and Thermal Management to ECP5 Using L-ASC10
FPGA-AN-020191.28/7/2023PDF2 MB
Adding Scalable Power and Thermal Management to MachXO2 and MachXO3 Using L-ASC10
FPGA-AN-020111.210/11/2019PDF2.1 MB
Dual Boot and Background Programming with PlatformManager 2
FPGA-TN-020781.310/10/2019PDF1.9 MB
Extending the VMON Input Range of Power/Platform Management Devices
FPGA-AN-020312.59/21/2021PDF1.1 MB
Fault Logging Using Platform Manager 2
TN12772.11/5/2018PDF3.5 MB
Implementing VID Function with Platform Manager 2
AN60921.29/8/2017PDF2.9 MB
Importing HDL Files With Platform Manager 2
TN12871.08/1/2014PDF546.9 KB
Interfacing the Trim Output of Power Manager II Devices to DC-DC Converters
AN60741.24/7/2015PDF3.1 MB
L-ASC10 and Platform Manager 2 Hardware Checklist
FPGA-TN-021751.21/27/2020PDF1.1 MB
Platform Manager 2 PM Bus Adapter Usage
TN12971.02/11/2015PDF2.1 MB
Powering Up and Programming Platform Manager 2 and L-ASC10
AN60912.13/31/2015PDF2 MB
Temperature Monitoring and Fan Control with Platform Manager 2
FPGA-TN-020801.29/30/2018PDF2.6 MB
Using Power MOSFETs with Power/Platform Management Devices
AN60481.38/29/2017PDF734.6 KB
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Package Diagrams
FPGA-DS-020538.58/5/2025PDF9.4 MB
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Platform Manager 2 Evaluation Board User Guide
EB931.07/30/2015PDF7.3 MB
Platform Manager 2 I2C Demo Design and GUI
UG591.18/11/2017PDF5.2 MB
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MachXO2/MachXO3/LPTM21 WISHBONE Flash Corruption Avoidance
PB13811.11/3/2017PDF88.9 KB
Work-around Solution for Platform Manager 2, MachXO2, and MachXO3 in SPI Programming Failure Modes
PB2311011.01/11/2024PDF372.2 KB
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PCN 09A-16_L-ASC10 I2C Datasheet
Data Sheet
PCN09A-166/13/2016PDF96.9 KB
PCN01A-15: LPTM20 Withdrawal
Data Sheet
PCN01A-154/28/2015PDF123.4 KB
PCN01A-18 - L-ASC10 and LPT2M Alternate Qualified Mask Set
PCN01A-18A4/18/2018PDF209.9 KB
PCN08A-19 Platform Manager 2 and L-ASC10 Data sheet Update
1.010/1/2019PDF285.3 KB
Power Calculator Update for All XO2 and Derivative (XO2/XO3L/XO3LF/XO3D/PlatformManager2) Devices
PCN02A-201.11/14/2021PDF28.6 KB
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Lattice OrCAD Capture Schematic Library
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
FPGA-SC-020059.012/16/2025ZIP3.2 MB
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Lattice FPGA Product Selector Guide
v25.3.01/6/2026PDF717 KB
Platform Manager 2 Brochure
I02362.04/21/2017PDF2.6 MB
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FTG237_LPTM21
Rev J16/9/2022PDF141.9 KB
Lattice Platform Manager 2 Product Family Qualification Summary
Rev F4/15/2020PDF729.9 KB
SN_SG48
Rev C19/20/2019PDF52.9 KB
TG128_DD
Rev D4/13/2018PDF22.1 KB
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Revolutionary Hardware Management Solutions
WP00034.05/9/2018PDF1.4 MB
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[BSDL] LPTM21L 100-caBGA
FPGA-MD-021010.807/2/2025ZIP4.7 KB
LPTM21_ftbga237
1.012/1/2014BSM29.3 KB
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[IBIS] L-ASC10
1.17/21/2020IBS116.6 KB
[IBIS] LPTM21
1.05/27/2015ZIP9.8 MB
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Platform Manager 2 I2C GUI
1.110/7/2014ZIP3.3 MB

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