Tablets

Driving Exceptional User Experiences In Next Generation Tablets

Related Products

Tablet architecture continues to evolve, adding more sensors, improving quality of existing sensors and displays which drive better user experience with crisp imagery and perfect details. In addition, device manufacturers are racing toward lower power consumption and slim size devices. Lattice FPGAs provide the bridging and distributed processing capabilities to elevate some of the challenges designer are facing on the road to innovative form factors with ultra slim designs.

Lattice’s solutions running on optimized low power FPGAs provide:

  • Flexible and low latency sensor data aggregation, bridging, data buffering and processing from a wide variety of sensors
  • MIPI CSI and DSI image sensor and display bridging
  • New form factors by improving board to board connectivity

Jump to

Block Diagram

Tablets

Example Use Cases

Sensor Fusion and I/O Expansion

  • Interface to a wide variety of sensors to create rich user experience
  • Flexible preprocessing including arbitration, time stamping, and filtering
  • Create programmable sensor fusion algorithms

Image Sensor Bridging

  • Connect wide a variety of image sensors to processors
  • MIPI PHY supports up to 2.5 Gbps/lane, up to four lanes
  • Flexible host interfacing including CSI, SPI, and PCIe
  • Flexible processing for video data muxing and Stitching

Display Bridging

  • Bridge between displays and processors when display interface is not supported native by the processor
  • Use the FPGA internal memory resources for compression and buffering
  • Expand the number of processor display interfaces

Reference Designs

Key Phrase Detection Reference Design Block Diagram

Reference Design

Key Phrase Detection

Continuous searches for a key phrase utterance via a digital MEMS microphone. Can be re-configured to work with any trained word or phrase.
Key Phrase Detection
Human Face Identification Reference Design Block Diagram

Reference Design

Human Face Identification

Uses a Convolutional Neural Network in the ECP5 FPGA to detect a human face, and match to known registered faces. Can be adapted to work with any other object.
Human Face Identification
Human Presense Detection Reference Design Block Diagram using iCE40 UltraPlus

Reference Design

Human Presence Detection

Uses Lattice sensAI IP to continuously search for the presence of a human and reports results. Can be adapted to detect any other object.
Human Presence Detection
Object Counting Reference Design Block Diagram using CrosLink-NX

Reference Design

Object Counting

An example object counting application based on the Lattice sensAI stack. Includes SPI, DDR IP blocks, ISP engine, 8 CNN engines and a counting / overlay engine
Object Counting
N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation with CertusPro-NX Block Diagram

Reference Design

CertusPro-NX N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation

Modular MIPI/D-PHY Reference Design - Multiple channel image data concatenated horizontally line by line and offers up to eight-channel aggregation.
CertusPro-NX N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation

Demos

Key Phrase Detection Block Diagram

Demo

Key Phrase Detection

Uses artificial intelligence (AI) to detect a specific key-phrase using a tiny, low-power iCE40 UltraPlus FPGA
Key Phrase Detection
CSI-2 PCIe Bridge Demonstration Block Diagram

Demo

CSI-2 PCIe Bridge Demonstration

This design demonstrates the functionality of transferring MIPI CSI-2 camera video data to computer via PCIe with a Direct Memory Access (DMA) engine.
CSI-2 PCIe Bridge Demonstration
Face Tracking Block Diagram

Demo

Face Tracking

ECP5 based Convolutional Neural Network (CNN) for face tracking with 8 convolution layers implemented in 8 Neural Network (NN) engines on ECP5-85K FPGA
Face Tracking
Human Counting Demo using CrossLink-NX

Demo

Human Counting

Human upper-body detection and counting demonstration utilizes Lattice’s ECP5 FPGA and a Convolutional Neural Network (CNN) acceleration engine
Human Counting

IP Cores

Convolutional Neural Network (CNN) Accelerator IP Block Diagram

IP Core

CNN Accelerator IP

Implement AI solutions with CNNs from common or custom networks. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
CNN Accelerator IP
CNN Block Diagram

IP Core

CNN Compact Accelerator IP

Implement AI solutions with CNNs or BNNs that have power consumption in the mW range. Works with Lattice Neural Network Compiler software tool.
CNN Compact Accelerator IP
CNN Plus Accelerator IP Block Diagram

IP Core

CNN Plus Accelerator IP Core

CNN Plus IP is a flexible accelerator IP that simplifies implementation of Ultra-Low power AI by leveraging capabilities of Lattice FPGAs.
CNN Plus Accelerator IP Core

Development Kits & Boards

CertusPro-NX Versa Board Side View

Board

Combined Side View

Board

Embedded Vision Development Kit

Three-board Video Interface Platform (VIP) modular kit. Includes 2 MIPI/D-PHY camera input, FPGA processing, HDMI output. More Input/Output boards available.
Embedded Vision Development Kit
CrossLink-NX Evaluation Board Side View

Board

CrossLink-NX Evaluation Board

For general evaluation and development with CrossLink-NX, includes many flexible interfaces such as FMC and PMOD with generous device IO access
CrossLink-NX Evaluation Board
HiMax HM01B0 UPduino Shield Side View

Board

Himax HM01B0 UPduino Shield

A complete development kit for implementing Artificial Intelligence (AI) using vision and sound as sensory inputs to a low-cost, low-power iCE40 UltraPlus FPGA.
Himax HM01B0 UPduino Shield

Support

Technical Support

Need Help? We're Here to Assist You

Quality & Reliability

Reference Material to Help Answer Your Questions