The Lattice Semiconductor CSI-2/DSI D-PHY Receiver IP Core converts DSI or CSI-2 data to 8-bit, 16-bit, 32-bit, or 64-bit data for Lattice FPGA devices built on the Lattice Avant™, Nexus™, and Nexus 2 platforms. The CSI-2/DSI D-PHY Receiver IP Core is intended for use in applications that require a D-PHY receiver in the FPGA logic. D-PHY Rx IP includes in both the high-speed and low power modules.
Latest Resource Utilization details are available in the IP Core User Guide.
Features
- Compliant with MIPI D-PHY v1.2, MIPI DSI v1.1, and MIPI CSI-2 v1.2 specifications.
- Selection between Hard Rx D-PHY or Soft Rx D-PHY implementation. Hard Rx D-PHY is only available for CrossLink-NX devices.
- Supports MIPI DSI and MIPI CSI-2 interfaces up to 6 Gb/s for Soft D-PHY and up to 10 Gb/s for Hard D-PHY.
- Supports 1, 2, 3, or 4 data lanes and one clock lane
