The Lattice Semiconductor FPD-Link Receiver IP translates video streams from a processor with an OpenLDI/FDP-Link/LVDS interface connection to the pixel clock domain. This IP can be used to connect with other application interfaces, such as the Mobile Industry Processor Interface (MIPI®) Display Serial Interface (DSI), by integrating it with the Pixel-to-Byte Converter and CSI-2/DSI D-PHY Transmitter IP cores.
Resource Utilization details are available in the IP Core User Guide.
Features
- Compliant with Open LVDS Display Interface (OpenLDI) v0.95 specifications.
- Receives in OpenLDI unbalanced operating mode format.
- Supports RGB888 and RGB666 video formats.
- Supports receiving in Dual Channel Flat Panel Display Link protocol (7:1 LVDS).
- Supports three to four LVDS data lanes per channel.
