The Tightly-Coupled Memory (TCM) IP ensures low-latency automatic selection of the best memory type for user-selected application. The design is implemented in Verilog HDL.
Resource Utilization details are available in the IP Core User Guide.
Features
- Configurable as single-port or dual-port memory
- The Core memory can be implemented as EBR , LRAM or Distributed RAM
- Supports the ROM and the RAM mode
- Supports configurable byte enables
- Supports byte writes when used with compatible hardware
