The HDR-60 Video Camera Development Kit is a fully production-ready High Dynamic Range (HDR) camera, designed to fit into commercially available camera housings. The hardware is intended to support full 1080p resolution at 60 frames per second in streaming mode through the FPGA, without the need for an external frame buffer.
The integrated IONOS Image Signal Processing (ISP) IP pipeline from Lattice partner Helion GmbH provides end-to-end ISP support from sensor to displayable image and incorporates sensor interfacing, defective pixel correction and 2D noise reduction, high-quality 5 x 5 DeBayer, Color Correction Matrix, Fast Auto Exposure, Auto White Balance, HDR, Gamma Correction and Overlay (both character and graphics). Lattice HDMI PHY IP enables output to HDMI/DVI monitors.
The HDR-60 Video Camera Development Kit provides the industry’s fastest Auto-Exposure, very high quality Auto White Balance and HDR greater than 120dB. On-board Broadcom Broadreach™ PHY enables support for Ethernet over coax up to a length of 700 meters. The hardware can support up to 16-megapixel sensors, can hold up to two sensors simultaneously and can be easily programmed via a standard low-cost USB cable.
The Kit consists of two boards, the long HDR-60 Base Board and the square Nanovesta Sensor Board mounted on top of the Base Board. The base board is populated with a LatticeECP3-70, while the sensor board is equipped with an Aptina 720p High Dynamic Range (HDR) sensor. The hardware, however, is designed to support full 1080p resolution at 60 frames per second.
The Kit incorporates a plug-n-play demo that runs right out of the box at 60fps when connected to a HDMI or DVI monitor. It is designed to jump-start the design efforts of camera manufacturer's planning to take advantage of the high-performance and low-power digital signal processing capabilities of Lattice FPGAs, the demo bitstream, board schematics and Gerber files that are available and free of charge to all purchasers of the Kit.
While the Kit is populated with a LatticeECP3-70 in order to provide ample space for a camera manufacturer's integration of their own IP, the entire IONOS HDR Image Signal Processing (ISP) pipeline is capable of fitting into a LatticeECP3-35 device. This, coupled with the fact that the ISP pipeline needs no external frame buffer as well as the low power consumption of the LatticeECP3 FPGA, means that HDR-60 based cameras are extremely low cost to build and operate.
