What’s New in Propel 2026.1
Discover what’s new in Lattice Propel 2026.1, featuring enhancements that improve user experience and streamline intuitive design creation. Watch now to see how the latest updates help you build FPGA-based embedded systems faster and focus on innovation.
Date: June 26, 2026 (English) Watch Now
What’s New in Radiant 2026.1
Lattice Radiant 2026.1 is purpose-built to help designers maximize productivity for small and mid-range FPGA designs. This release turbocharges development speed and drives unparalleled usability.
Date: June 26, 2026 (English) Watch Now
FPGA‑accelerated 3D Sensing for Humanoid Robot Manipulation
This demo showcases a miniaturized 3D sensor module built on AIRY3D’s patented TDM technology, mounted on a humanoid robotic arm and interfaced with the Lattice CrossLink™-NX 40 FPGA. The FPGA offloads the majority of depth computation, reducing system load and enabling efficient operation alongside an application processor such as the NVIDIA Jetson Orin™ Nano. With a wide field of view and no occlusion, the sensor delivers accurate near‑field depth awareness. This capability opens new opportunities for robotic grasping, in‑hand manipulation, and end‑effector‑mounted perception, supporting more responsive and intelligent humanoid robotics systems.
Multi‑sensor 10GbE Aggregation for NVIDIA Holoscan Using Lattice FPGAs
This demo highlights the DA322 Holoscan Adapter from Tauro Technologies, a compact multi‑sensor aggregation platform built on a low power Lattice CertusPro™‑NX FPGA. The solution supports four MIPI CSI‑2 camera inputs and aggregates HDMI, MIPI, or GMSL data into a single 10 GbE stream for efficient sensor ingest. Using RDMA, the platform feeds synchronized, high‑bandwidth data directly into NVIDIA Orin™ or Thor™ systems for real‑time visualization. With Precision Time Protocol (IEEE 1588‑2019), flexible multi‑function I/O, and an SFP+ 10 Gbps interface, the design enables scalable, space‑efficient sensor integration for advanced edge AI and visualization applications.
Real‑time 4K30 Embedded Vision Pipeline on Lattice Avant™ FPGAs
This demo showcases a real‑time 4K30 imaging pipeline implemented on the Lattice Avant FPGA platform, highlighting a complete embedded vision workflow from sensor input through FPGA‑based ISP processing to low‑latency HDMI output. The design demonstrates how Lattice Avant enables high‑performance, modular image signal processing that can be adapted to application‑specific requirements while maintaining real‑time operation. Designed for evaluation, rapid prototyping, and scalable camera development, the solution illustrates the flexibility and performance of Lattice Avant for next‑generation embedded vision systems.
Multi‑camera Aggregation for Real‑time Edge AI on Lattice Avant™ FPGAs
This demo showcases a scalable multi‑camera aggregation architecture using a Lattice Avant‑X FPGA and NVIDIA Hololink™ technology to enable ultra‑low‑latency sensor ingest for edge AI systems. Multiple camera streams are synchronized, aggregated, and preprocessed on the FPGA before being transmitted over standard 10 G or 25 G Ethernet to NVIDIA Thor™ for real‑time AI processing. By offloading camera handling, timestamping, and data conditioning from the host, the design reduces system overhead while delivering high‑bandwidth, deterministic performance. The demo highlights an AI‑ready pipeline optimized for demanding applications such as ADAS, robotics, aerospace, defense, and industrial vision.
SLVS‑EC 3.1 Image Sensor Interface on Lattice Avant™ FPGAs
This demo showcases an SLVS‑EC 3.1 image sensor interface implemented using Macnica’s SLVS‑EC IP on Lattice Avant-G and Avant-X FPGAs. Designed to support the latest Sony SLVS‑EC image sensors, the solution enables high‑performance, low‑power image capture in a compact FPGA footprint. The design supports backward compatibility with earlier SLVS‑EC standards, flexible pixel widths, multiple lane configurations, and ECC for secure data transmission. With built‑in features such as de‑skew and byte‑to‑pixel conversion, the demo highlights how Lattice Avant FPGAs simplify system design and accelerate evaluation of next‑generation high‑resolution imaging applications.
Aurora to 10G Ethernet Protocol Conversion on Lattice Avant™ FPGAs
This demo showcases an FPGA‑based protocol conversion solution from Lattice partner A.L.S.E that bridges Aurora high‑speed serial links to standard 10G Ethernet. Targeting imaging and data acquisition systems where Aurora is commonly used for low‑latency, high‑bandwidth data transfer, the design demonstrates a scalable alternative to custom PCIe boards for PC connectivity. Using a Lattice Avant Versa kit with dual SFP+ interfaces, the solution converts Aurora traffic to 10G Ethernet, simplifying system integration while maintaining performance and flexibility across heterogeneous protocols.
Single‑Chip EtherCAT® Motor Control on Lattice FPGAs
This demo showcases an integrated EtherCAT motor control solution implemented on a single Lattice FPGA, designed for real‑time motion control nodes in industrial automation systems. The design combines cyclic EtherCAT process data exchange with a deterministic field‑oriented control (FOC) motor control subsystem, delivering high‑dynamic performance with minimal latency. An embedded RISC‑V processor manages configuration and application control, while single‑chip integration consolidates EtherCAT communication, the FOC control loop, and encoder interfaces to reduce BOM, save board space, and improve system determinism.
Low Power PQC‑enabled FPGA and TPM Platform for Secure Physical AI
This demo showcases a joint Lattice, SEALSQ, and Promwad reference board designed to accelerate development of secure physical AI and industrial control systems. The platform combines a low power Lattice FPGA acting as a Root of Trust with a SEALSQ post‑quantum cryptography (PQC)‑compliant TPM, enabling secure boot, device attestation, and ongoing cyber‑resilient monitoring. With support for TPM 2.0 PQC extensions, anti‑tamper protection, and real‑time deterministic control, the reference design provides a practical foundation for building future‑ready systems that require strong security, flexibility, and rapid prototyping.
10BASE‑T1S Network Interoperability Demo on Lattice CertusPro™‑NX
This demo presents a 10BASE‑T1S Ethernet network evaluation platform developed with Canova Tech, showcasing throughput and interoperability across a mixed‑topology network. The design integrates Canova Tech’s 10BASE‑T1S Digital Controller IP synthesized on a Lattice CertusPro‑NX FPGA, with logic boards implementing MAC functionality, data handling, and control logic. A microcontroller manages system initialization, configuration, and MAC‑PHY interaction through standard interfaces, including OPEN Alliance and Media Independent Interface (MII). Together, the solution demonstrates a practical approach for validating 10BASE‑T1S Ethernet in automotive and industrial networking environments.
Full‑Bridge PCIe® Demo with NXP Hosts and Lattice Certus™ FPGAs
This demo highlights Lattice’s full‑bridge PCIe IP implemented on a Lattice Certus FPGA and demonstrated with NXP host processors. The FPGA appears as a standard PCIe endpoint with memory‑mapped BAR space, while also acting as a bus master capable of initiating transactions back to the host. A configurable application layer and embedded RISC‑V processor showcase mailbox‑based command handling, register access, and host‑to‑flash programming and verification over PCIe. By eliminating the need for an external bridge device, the design demonstrates how a single PCIe link enables efficient, bidirectional communication and remote update capabilities in NXP‑based systems.
BMC Board Demo
The BMC Board Demo showcases a flexible and scalable Baseboard Management Controller (BMC) solution jointly developed by Lattice, NXP, and Antmicro. Running on the Intel Birchstream platform, the demo integrates an NXP i.MX94 MPU and a Lattice MachXO5™-NX 55TDQ FPGA on a compact SOM module to implement OpenBMC functionality. This reference design supports fan control, sensor management, and remote access, and is plug-and-play compatible with any DC-SCM server. The Lattice FPGA acts as a sensor aggregator, hardware abstraction layer, and Root of Trust, while the open-source hardware and software stack eliminates the need for custom BSP development—offering a modular, future-proof approach to server management.
Dual HPM Single SCM LTPI Demo
This demo showcases a high-performance LTPI setup using a single System Control Module (SCM) connected to two Host Processor Modules (HPMs) via the Lattice MachXO3™ device. It demonstrates efficient aggregation of low-speed signals—GPIO, UART, and I2C—from the SCM to both HPMs, with real-time link status monitoring and environmental sensing. Each LTPI link operates independently, ensuring uninterrupted CPLD functionality even if one HPM disconnects.
Lattice PQC Solution for Lattice MachXO5™-NX 55TDQ and PFR Demo
This demo highlights Lattice Semiconductor’s industry-first PQC-ready secure control FPGA, the Lattice MachXO5-NX 55TDQ, showcasing a single-chip solution that integrates attestation verifier, Platform Firmware Resiliency (PFR), and LTPI capabilities. Built on the power-efficient Lattice Nexus™ platform, the demo demonstrates robust post-quantum cryptography (PQC) support compliant with CNSA 2.0 and NIST standards, including ML-KEM and ML-DSA algorithms. It emphasizes crypto-agility, secure boot, hardware root of trust, and hybrid security models—making it ideal for datacenter, industrial, and communications infrastructure applications.
MPESTI Interoperability with Nuvoton and Renesas Fanout Controller Demo
This demo showcases Lattice Semiconductor’s implementation of the Modular Peripheral Sideband Tunneling Interface (MPESTI), a single-wire communication protocol developed under the Open Compute Project (OCP). It highlights seamless interoperability between a MPESTI Initiator and multiple target devices from Nuvoton and Renesas, connected via a fanout controller on the Lattice iCE40 UltraPlus™ board. The setup supports up to 64 endpoints, enables hot-plug capability, and eliminates the need for external MUX or switches—offering a scalable, cost-efficient solution for modular data center environments.
Onboarding LTPI Demo
The Onboarding LTPI Demo showcases Lattice’s seamless Plug and Play setup for Host Processor Module (HPM) endpoints using JSON-based onboarding. It highlights how LTPI bridges hardware differences between HPM and DC-SCM modules by combining I2C, UART, and GPIO into a unified high-speed interface. The demo features dynamic metadata capture, pre-link endpoint detection via a RISC-V I2C controller, and sensor interaction through a Raspberry Pi acting as a BMC—demonstrating scalable, interoperable integration for modern data center ecosystems.
Quantum Secure Key Exchange Demo
This demo showcases the establishment of a quantum-resistant secure communication channel using post-quantum cryptography (PQC) on the Lattice MachXO5™-55TDQ FPGA. It features ML-KEM for key exchange and ML-DSA for digital signing, simulating secure boot, mutual authentication, and encrypted data exchange over I2C. The setup includes pre-provisioned public keys, protection against impersonation and replay attacks, and aligns with SPDM 1.4 standards. Designed for crypto agility, the demo highlights Lattice’s commitment to future-proof firmware security in datacenter, industrial, and communications applications.
SEC-TPM with Lattice MachXO5™-NX
The SEC-TPM Demo showcases a single-chip Root of Trust solution, integrating traditional TPM functionality with post-quantum cryptography (PQC) and Platform Firmware Resilience (PFR). Running on a RISC-V core, the demo highlights secure credential management anchored to hardware, leveraging Lattice’s RNG and crypto-agile architecture. It eliminates the need for external TPM chips, simplifying the supply chain and enabling secure remote updates—making it ideal for next-generation server security applications.
Single Chip Solution for Attestation Verifier, PFR, and LTPI Demo
This demo showcases Lattice’s unified security solution built on the Lattice MachXO5™-NX 55TDQ device, integrating attestation verifier, Platform Firmware Resilience (PFR), and LTPI capabilities into a single chip. Leveraging the Lattice Sentry™ 4.0 platform, it supports both traditional cryptography and post-quantum algorithms (ML-DSA, ML-KEM), enabling secure image authentication, key exchange, and encrypted communication. The solution is compliant with SPDM 1.2, NIST 800-193, and CNSA 2.0 standards, and offers robust connectivity via I2C, I3C, SMBus, and LTPI—delivering scalable, crypto-agile protection for modern server platforms.
SPDM 1.2 Demo
The SPDM 1.2 Demo showcases the Lattice Sentry™ 4.0 platform’s robust hardware and firmware security capabilities through cryptographic attestation. Running on the Lattice MachXO5™-NX 55TDQ device, the demo verifies device identity and firmware integrity using SPDM 1.2 commands over I2C and I3C interfaces, including LTPI channels. It highlights a modular framework designed for future security upgrades, including SPDM 1.4 and post-quantum cryptography (PQC) with ML-KEM and ML-DSA support—demonstrating Lattice’s commitment to evolving cybersecurity standards.
USB to I/O Conversion Demo
The USB to I/O Conversion Demo showcases Lattice’s high-speed USB 2.0 connectivity solution built on the Lattice CrossLinkU™-NX FPGA, enabling seamless bridging between modern computing platforms and essential peripherals like GPIO, UART, and I2C. Supporting both CDC and MCTP USB classes, the demo highlights a scalable multi-endpoint architecture that manages up to three USB devices, ensuring robust system management and protocol flexibility. Designed for multi-node environments, this modular solution empowers developers with crypto-agile control and future-ready integration across industrial, embedded, and server applications.
Industrial HMI Demo: Intelligent Operator Recognition and Control
Experience a cutting-edge industrial human-machine interface (HMI) that features advanced operator attention sensing and identification. This demo enables seamless interaction with machinery, delivering real-time insights and precise control for enhanced operational efficiency.
Securing the Future: Cybersecurity Compliance and Global Standards
Learn the fundamentals of cybersecurity standards and regulations in this informative video. We break down the scope, key requirements, and essential security principles that organizations must follow to stay compliant and secure with leading agencies such as NIST, CISA, NSA, ENISA, ETSI, and the European Commission. Whether you're new to cybersecurity or looking to stay updated on regulatory expectations, this video provides a concise overview to help you navigate the landscape with confidence.
Lattice Semiconductor: Advancing Low Power FPGA Leadership
As the low power programmable leader, Lattice is at the forefront of FPGA innovation. We're committed to delivering industry-leading low power, high-performance, small footprint solutions as a steadfast, trustworthy partner to our customers worldwide.
Lattice Nexus™ 2 FPGA Platform
What’s New in Lattice Radiant™ 2024.2
Lattice Nexus™ 2 FPGA Platform: Power and Performance Leadership Demonstration
Lattice Nexus™ 2 FPGA Platform: Boot Up Demonstration
Lattice Nexus™ 2 FPGA Platform: Edge Sensor Monitoring Demonstration
Lattice Avant™-X FPGA: SERDES Demo
Lattice Avant™-X FPGA: Power Efficiency Demo
Lattice Avant™-G FPGA: Boot Up Time Demo
Glance by Mirametrix® Demonstration: Enhancing Safety and Reducing Errors in Industrial Applications
2023 Lattice Developers Conference: Opening Keynotes
Innovative Mid-Range FPGAs: Lattice Avant™-G and Lattice Avant™-X
Lattice Drive™ Solution Stack - Accelerate Automotive Application Development
Lattice Radiant – FPGA Design Complete Tools Suite
Lattice Semiconductor: Expanding Our FPGA Leadership
Accton Technology: Power Efficient FPGA Solutions, Lattice Avant™ Launch Event
NI: Power Efficient FPGA Solutions, Lattice Avant™ Launch Event
Rockwell Automation: Power Efficient FPGA Solutions, Lattice Avant™
Lattice Ecosystem Partners Share Excitement on Lattice Avant™
Lattice Avant™ FPGA Platform: AI Processing Demo
Lattice Avant™ FPGA Platform: Performance Demo
Lattice Avant™ FPGA Platform: Power Efficiency Demo
Lattice Avant™: The Next Level of FPGA Innovation
Lattice Avant™ FPGA Platform: Taking Low Power to New Heights
Lattice Semiconductor: Keynote Address at Embedded World 2022
Interview with Lattice Semiconductor: How FPGAs Solve Today’s Technology Trend Challenges
Introducing the Lattice Nexus Platform
Introducing CrossLink-NX
CrossLink-NX: Power Efficiency Demo
CrossLink-NX: Instant On Demo
Lattice Semiconductor: the low power programmable leader
Lattice MachXO3D: accelerating development of secure systems
Lattice sensAI: accelerating low power AI at the edge
Using eARC to Easily Enable Theater Quality Surround Sound
This video introduces the benefits of HDMI 2.1’s eARC feature:
- Higher bandwidth – 37M of audio that supports all audio formats
- Full home theater experience with the simplicity of operating a TV set
- Future proof receivers against changes in video standards
Building a Seamless 360 Degree Surround View with ECP5
This demonstration takes the output from four fish-eye cameras and performs de-warping, white balance correction, and image stitching. The demonstration also enables the user to provides different views.
Face Tracking Using ECP5 and CNNs | Lattice sensAI
This demonstration identifies and tracks a human face. The inferencing is done using Convolutional Neural Networks implemented in the Embedded Vision Development Kit’s ECP5 FPGA. Power consumption is less than 1W.
Human Presence Detection Using ECP5 and CNNs | Lattice sensAI
This demonstration processes video images and identifies the presence of a human. The inferencing is done using Convolutional Neural Networks implemented in the Embedded Vision Development Kit’s ECP5 FPGA. Power consumption is less than 1W.
Object Counting Using ECP5 and CNNs | Lattice sensAI
This demonstration tallies apples and oranges to demonstrate object counting. The inferencing is done using eight Convolutional Neural Networks implemented in the Embedded Vision Development Kit’s ECP5 FPGA. Power consumption is less than 1W.
Speed Sign Detection Using ECP5 and CNNs | sensAI
This demonstration looks for speed limit signs and interprets what is on the sign. The inferencing is done using Convolutional Neural Networks implemented in the Embedded Vision Development Kit’s ECP5 FPGA. Power consumption is less than 1W.
Fast Prototyping for Embedded Vision Applications
Learn how easy it is mix and match multiple I/O types with the modular VIP platform.
- Input options: HDMI, DisplayPort, Dual Sensor
- Output options: HDMI, DisplayPort, USB3-GbE
Using CrossLink to implement a MIPI DSI to LVDS bridge
Always-on Computing Demos from Lattice Semiconductor
Lattice GigaRay 60 GHz Wireless Modules
Using Lattice CrossLink FPGA for 360 Surround View Applications
Enable Predictable Design Convergence with Lattice Radiant Software
Lattice Autonomous Robot Demo
Simplify Audio Connectivity with HDMI 2.1 eARC
CrossLink IP Cores for Mobile Influenced Markets
Lattice Wireless Infrastructure Solutions
Service providers working on the implementation of metro Wi-Fi, LTE small cell for backhaul, or next-gen wireless mesh networks can benefit from Lattice's wireless solutions, built with SiBEAM 60 GHz technology. Our beam-steering feature does not require precise alignment to establish links.
Lattice Embedded Vision Development Kit
We have combined the bridging capability of our CrossLink FPGA, the low-power, small form factor ECP5 and the high-resolution benefits of our HDMI ASSP, onto this modular platform. Learn about the specs of this development kit and let us help you enable flexible connectivity and energy efficient image processing for robotics, drones, ADAS, smart surveillance and AR/VR systems.
LATTICE at Embedded World 2017
Lattice Semiconductor showcases product solutions for connectivity and processing at the edge.
CrossLink 4:1 CSI-2 Aggregator IP Demo from Lattice Semiconductor
Learn more about Lattice's CrossLink FPGA and its new 4:1 MIPI CSI-2 camera aggregator bridge, ideal for drones, AR/VR, 360 cameras, and other automotive and industrial solutions.
Embedded Vision Solutions using Lattice Semiconductor Products
Learn how Lattice products support edge computing applications (video processing acceleration), sensor bridging for machine vision, and stereo vision for robotics and drones.
FPGAs in Automotive
Learn how FPGAs can support the needs of modern Advanced Driver Assistance Systems (ADAS) .
Stereo Vision for Robotics using Lattice Semiconductor Products
Lattice CrossLink FPGA, ECP5 FPGA and HDMI ASSP come together to provide one clean and efficient solution for video processing and delivery.
Lattice Automotive Solutions for ADAS
Using Lattice’s ECP5 FPGA device, we are able to take the images of multiple automotive cameras, stitch them together, and apply many enhancing/correcting benefits to output one final, clean image for the driver.
Signal Aggregation Solutions with Lattice iCE40 FPGAs
The iCE40 UltraPlus is the world’s smallest FPGAs with enhanced memory & DSPs for reduced system cost, lower power consumption & faster time-to-market. Our sensor data fusion with embedded RISC-V and multi-sensor aggregation demos show why iCE40 UltraPlus is a must for your next consumer device.
Signal Aggregation using Lattice Solutions
We are demonstrating video and audio signal aggregation in products using Lattice iCE40 FPGAs.
Signal Aggregation Solutions with Lattice iCE40 FPGAs
The iCE40 UltraPlus is the world’s smallest FPGAs with enhanced memory & DSPs for reduced system cost, lower power consumption & faster time-to-market. Our sensor data fusion with embedded RISC-V and multi-sensor aggregation demos show why iCE40 UltraPlus is a must for your next consumer device.
Lattice iCE40 UltraPlus Benefits Demo
Meet iCE40 UltraPlus, the first iCE40 product supporting MIPI D-PHY with LP and HS modes. Learn about additional benefits, like driving a MIPI DSI display along with integrated SRAM memory for frame buffering, in this video.
Multi CSI-2 Bridge for Camera
Whenever the interface on a camera does not match that of the application processor, a bridge is required. A common application example is muxing or merging multiple MIPI CSI-2 image sensors and combining them to one MIPI CSI-2 output. The CrossLink solution is a camera aggregator used for drones, 360 cameras, action cameras, surveillance and augmented reality applications.
ECP5 - FPGA Family
The ECP5 FPGA Family breaks the rule that all FPGAs should be the highest density, power hungry, and expensive. With a focus on compact, high volume applications, Lattice optimized the ECP5 architecture for low cost, small form factor and low power consumption. These characteristics make the ECP5 devices ideal for delivering programmable connectivity solutions to complement ASICs and ASSPs.
USB Type-C
To enable demonstrations of our USB Type-C solutions to potential customers we have recorded a short video showing our product working as a UFP, DFP and DRP.
SiBEAM Snap
Introducing SiBEAM Snap Technology that will changes the way you connect your devices.
MachXO2 - Overview
See an overview of the MachXO2 product family. Learn how MachXO2 lowers cost, lowers power and integrates system functionality, all in a small package. See how easy it is to start designing with MachXO2 devices with free design tools, IP trials & reference designs.
Adding CrossLink IP Using Clarity Designer
What’s New in Lattice Radiant 2025.2
Lattice Radiant 2025.2 focuses on improvement in debugging, ease of use and designer productivity. Download Radiant now to explore more features.
What’s New in Lattice Propel 2025.2
Lattice Propel 2025.2 focuses on improved design creation and accelerated project startup. Download Propel now to explore more features.
