Lattice Propel Version History

• New Operating System (OS) Support
  • Red Hat Enterprise Linux 9.6 (64-bit)
• Tools and Enhancements
  • Supports automatic interconnection between controllers and targets, featuring intelligent pathfinding via unified interconnect IP.
  • Supports address allocation for restricted EM-to-ES path connections via unified interconnect IP setting.
  • Enables address-space-aware interface export without requiring Feedthrough IP.
  • Supports exporting Propel SoC Project into existing Radiant Project.
  • Supports automatic mapping between physical and logical ports in IP Packager.
  • Enables VHDL-2008 support in IP Packager.
  • Supports adding new port types – Reset/Clock, and clock frequency consistency check for Clock port.
  • Provides a new JTAG Bridge Demo template for on-board debugging, enabling access to memory and peripheral registers through the JTAG Bridge IP.
  • Supports renaming components in the SoC design.
  • Supports for RISC-V MC and SM core on-chip debugging on LFMXO4.
  • Added an easy-to-access toolbar to the schematic top view.
  • Added board information and URL link to the board-level Scalable RISC-V SoC Project creation flow.
  • Improved TCL “ip_catalog_list” to list all available IP without opening an SoC project.
  • Migrated Low Power Project and RISC-V RX SHA-3 CXU Project to Scalable SoC flow with unified interconnect IP.
  • Improved Start Page to provide quick access to SoC project creation, built-in tools, and documentation links.
  • Refined the scope of undo and redo operations.
  • Refined the list of RISC-V registers in the Console and Register views of the Propel SDK debugger.
  • Supports Red Hat Enterprise Linux 9.6 (64-bit) OS.
  • Installer enhancement for NFS mount installation in Linux OS.
  • Miscellaneous bug fixes. 

• New Device Support
  • Lattice LFMXO4 (MachXO4)
• New Operating System (OS) Support
  • Red Hat Enterprise Linux 8.10 (64-bit)
  • Ubuntu 24.04 LTS (64-bit)
• Tools and Enhancements
  • Provides a utility to create firmware of reference design for Lattice Bootloader.
  • Provides Bootloader for lattice RISC-V processor.
    • For Scalable RISC-V RX SoC Project:
      • Bootloader Launch Firmware from SPI Flash Project
      • Bootloader Launch Firmware in XIP mode Project
  • Provides new IP application templates.
    • For Scalable RISC-V RX SoC Project:
      • I3C Communication Project
      • General Purpose Timer Project
      • SPI Controller Project (Updated Driver for Octal SPI Controller v1.3.0)
  • Refined the display of RISC-V registers in the Console and Register views of the Propel SDK debugger.
  • Supports address mapping for external IPs, including CPU, APB, AHBL, and AXI peripherals.
  • Supports TCL command autocompletion in TCL console.
  • Supports reinstantiating a component via undo.
  • Supports batch import of VHDL/Verilog RTL files for glue logic.
  • Added extra AHBL Data Bus interface and internal UART interrupt in RISC-V RX v2.8 core.
  • Added more peripherals to Scalable RISC-V RX SoC Project to demonstrate IP applications.
  • Supports running multi-instance Propel Builder with a single-seat license on one workstation.
  • Supports configuring Lattice Radiant and Lattice Diamond software locations for each Propel release.
  • Added a "Connection Editor" GUI for managing disconnections.
  • Added a tooltip in the IP configuration GUI to remind users that the IP source files will be updated.
  • Enhanced SoC memory data read/write via JTAG Bridge IP and Lattice HW-USBN-2B cable using TCL.
  • Enhanced SoC level DRC check to guarantee the clock consistency among all the components.
  • Enhanced automatic installation of missing IPs in Scalable SoC creation flow.
  • Enhanced usability of the Propel Builder cascade group.
  • Improved the balanced mode of RISC-V RX to 200 MHz for Lattice Avant Devices’ Speed Grade.
  • Enhanced the "What's New" page in Propel Builder.
  • Miscellaneous bug fixes and enhancements.

Tools and Enhancements

• Updated IP RISC-V RX from v2.6.0 to v2.7.0
• Updated IP TCM from v1.5.2 to v1.5.3
• Updated IP RISC-V MC from v2.8.0 to v2.8.1

• Provides new single-function application templates to demonstrate RISC-V capabilities
  • For Scalable RISC-V RX SoC Project:
    • Hardware Interrupt Project - PLIC
    • Real Timer Project
    • Software Interrupt Project
    • Watchdog Timer Project
  • For Scalable RISC-V MC SoC Project:
    • Mtimer Project
    • Hardware Interrupt Project – PIC
  • For Scalable RISC-V SM SoC Project:
    • Mtimer Project
  • Provides new IP application templates
    • For Scalable RISC-V RX SoC Project:
      • I2C Communication Project
      • SPI Controller Project
• Provides terminal_cli tool to support UART print on Linux OS using Lattice HW-USBN-2B cable
• Enabled the “Wframe-larger-than” warning for application templates to detect potential stack overflow issues during project compilation
• Provides RISC-V RX IP based Low Power Project to demonstrate and evaluate SoC low power mode
• Provides RISC-V MC Multi Processor Project to demonstrate multiple processor features
• Supports automatically parsing IP RTL to populate ports in IP Packager
• Supports automatic installation of missing IPs in Scalable SoC creation flow
• Added GUI support for “Upgrade All IPs” to display current and target IP versions
• Supports grouping instance in SoC schematic
• Supports project-level colour settings, overriding default colours for SoC schematics
• Supports porting designs from one device to another
• Supports SoC memory data read/write via JTAG Bridge IP and Lattice HW-USBN-2B cable using TCL
• Supports new SoC level DRC check to guarantee the clock consistency among all the components
• Supports GUI wizard to generate simulation environments
• Supports showing default values assigned to dangling sub-signals in the GUI
• Optimized INFO message on dangling ports and mismatched Bus width
• Improved the Validate Design message for clear success or failure indication
• Added What's New demo about some new features
• Enhancement for display of high-resolution screen
• Miscellaneous bug fixing and enhancements.

• Tools and Enhancements
  • Updates IP AHB Lite Interconnect from v1.3.2 to v1.3.3
  • Updates IP System Memory from v2.3.0 to v2.3.1
  • Fixes IP Packager issue on address space reference of AHB-Lite Interface
  • Fixes automatic 4k memory allocation to peripherals when AXI interconnect is added without connection
  • Supports installation in FIPS mode
  • Synchronized device, IP, and Questa Sim libraries to Radiant ng2024_2p.321

• New Device Support
  • Lattice ECP3
  • Lattice iCE40 UltraPlus (iCE40UP)
  • Lattice Certus™-N2 (LN2-CT)
  • Lattice Avant™ (LAV-AT), Certus™-NX (LFD2NX), and MachXO5™-NX (LFMXO5) new device variants
• Tools and Enhancements
  • Supports license debugger in Propel Builder.
  • Supports connections on individual ports within interfaces.
  • Supports scalable design flow to create SoC with multiple peripherals based on RISC-V processors.
  • Improved Builder Engine to only regenerate RTL when real modification on the design performed.
  • Adds IP Wrapper Creator tool to generate an empty IP wrapper with pre-defined ports and interfaces.
  • Supports IP generation before it gets packaged.
  • Adds IP information hyperlink in the Module/IP Block Wizard.
  • Supports IP availability check when opening an SoC design.
  • Supports automatic download and installation of sever IP to local IP Catalog when generate IP.
  • Improved Tcl inline help.
  • Adds more TCL command supports.
  • Supports logging Tcl history, organized by date, and displayed via a dedicated tab in Builder.
  • Adds Project Summary tab in Builder GUI with SoC opened in Builder.
  • Supports cacheable address range display in Address tab of Builder GUI.
  • Adds a new RISC-V Nano SoC Project to support RISC-V Nano core.
  • Adds version for newly added or updated templates.
  • Supports register access test on peripherals for connectivity check in scalable SoC design.
  • Supports custom application templates export as a zip archive.
  • Supports CXU demonstration usage in updated SHA3 CXU Template.
  • Supports standalone Code Coverage application template.
  • Extends the ability of the Application Template Framework to support advanced SDK features.
  • Supports SDK awareness of RISC-V extensions when creating or updating C/C++ projects.
  • Adds "Browse for System Environment XML" in creating C/C++ project.
  • Adds warning of inconsistent versions of Lattice Propel and Lattice Radiant™ software.
  • Supports PUR_INST in Lattice Diamond device simulation.
  • Miscellaneous bug fixes and enhancements.

• New Operating System (OS) Support
  • Ubuntu 22.04 LTS
• New Device Support
  • Lattice ECP5U™
  • Lattice ECP5UM™
  • Lattice ECP5UM5G™
• Tools and Enhancements
  • Supports user custom application templates
  • Supports TCL in IP Packager
  • Supports ECP5 and ECP5-5G devices
  • Supports Lattice Avant RISC-V MC/RX SoC templates
  • Supports "Attach to running target" in debugger
  • Supports GUI color customization options for schematic
  • Supports code coverage and timing profiling on RISC-V RX SoC Project
  • Supports an extension on C projects created for RISC-V RX SoC Project
  • Supports a new entry to distinguish SoC creation from custom templates or built-in templates
  • Supports QuestaSim instead of ModelSim
  • Supports DRC of generating default value in top RTL file for AMBA4 dangling optional ports
  • Supports DRC of cacheable address range on SoC including RISC-V RX processor
  • Supports DRC of connection compatibility between RISC-V RX processor and TCM
  • Supports VHDL for RTL module of glue logic
  • Supports friendlier interface names in IP Packager GUI Display
  • Supports QEMU Virtual Platform
  • Supports creating application template Hello World Project for RISC-V MC/SM/RX minimum system
  • Supports creating application template RX Demo Project for RISC-V RX minimum system
  • Supports creating default debug launch configuration when creating a C project
  • Supports enabling/disabling automatically build the project when creating a C project
  • Hides glue logics from verification project view
  • Supports read-only address map for verification projects
  • Adds a new entry of importing Lattice C/C++ Projects into Workspace
  • Adds application template FreeRTOS-LTS-Minimal Project
  • Former FreeRTOS Project is renamed to FreeRTOS-LTS PMP-Blinky Project
  • FreeRTOS Kernel update from v10.0.1 to v10.5.1 based on FreeRTOS 202210.01 LTS

• Tools and Enhancements
  • Synchronized device, IP, and Questa Sim libraries from Radiant.
  • Miscellaneous bug fixes.

• New Operating System (OS) Support
  • Red Hat Enterprise Linux 7.9 (64-bit)
  • Red Hat Enterprise Linux 8.8 (64-bit)
• Tools and Enhancements
  • Supports consistent interface for creating SoC project from Propel Builder and Propel SDK
  • Supports new C project flow to create different example application projects
  • Supports reproducing customized templates from Propel SDK
  • Supports Heap_4 and user-defined priority for task_create in FreeRTOS reference C project
  • Supports the Updating Lattice C/C++ Project flow for RISC-V MC Dual Processor Project
  • Supports soft JTAG debug for LFCPNX device
  • Supports F extension on RISC-V RX IP Core
  • Supports generation of a file list for scripted build flows
  • Supports IP upgrade/configure through TCL commands
  • Supports switching design output language between Verilog-HDL and VHDL after initial project creation
  • Supports exporting SoC as a set of TCL command and recreating from it
  • Supports DRC for mismatched ID/DATA width in AXI4, AHB Lite, and APB interfaces
  • Supports simulation for design with VHDL
  • Supports simulation for RISC-V RX core templates
  • Supports DUT with one-level sub sbx in verification project
  • Installer enhancements for Windows and Linux platforms

• New Operating System (OS) Support
  • Microsoft Windows 11 (64-bit)
  • Red Hat Enterprise Linux 8.6 (64-bit)
• New Device Support
  • LFCPNX-50 (CertusPro™-NX)
  • LFMXO5-55T (MachXO5™-NX)
  • LFMXO5-100T (MachXO5-NX)
• Tools and Enhancements
  • Supports soft JTAG (so far only applied on Avant Hello World Project and Avant FreeRTOS Project).
  • Supports IP driver version tracking.
  • Supports software data watchpoint.
  • Supports input ports, output ports, and glue logic to be connected to inout ports.
  • Supports using TCL command line to clear Tcl Console, create SoC, reconfigure glue logic, connect grouping signals.
  • Supports Auto Connect grouping signals.
  • Supports reference IP RTL from user-specified library in IP Packager.
  • Supports generation and reconfiguration of IP from a centralized IP repository.
  • Supports subordinate sbx for design simplification and memory map display.
  • Improves customized templates with constraint file included.
  • Optimizes warnings and disables modifying Propel IP in Lattice Radiant software.
  • Added warning message for glue logic RTL that has been updated since it was originally added.
  • Previous Propel software versions available on Software Archive page on Company Public website: https://www.latticesemi.com/Support/SoftwareArchive