Hand Gesture detection in smart IoT devices – This demo uses artificial intelligence (AI) to implement hand gesture detection algorithm. FPGAs have parallel data processing ability, making them more power efficient at such tasks compared to a microprocessor.
Always-on, local intelligence improves security – Designing AI to the network edge with an iCE40 UltraPlus FPGA can dramatically lower power consumption for always-on operation while reducing response time. Keeping processing local also improves security.
Compact CNN in a tiny FPGA – The Lattice inference engine with VGG like CNN architecture is implemented in a 48-pin QFN package on a low cost UPduino 2.0 board.
Features
- Accelerated, low-power hand gesture (open/close) detection at the network edge using neural network model
- Configuration files enable rapid implementation on UPduino 2.0 board with Himax HM01B0 image sensor
- Input resolution of 32x32x1 connects to a VGG like CNN with 6 convolutions, 4 max pooling and fully connected layers
- With integrated 128 K bytes of memory, weights/activations can be stored directly inside of iCE40 UltraPlus FPGA
- Power consumption of 3.3 mW @ 5 frames per second. The reference design can be optimized between power and response time depending on system needs
- The neural network can be retrained to detect other gestures
This demo runs on the Himax HM01BO IPduino Shield board.
