PAC-Designer Design Software

Powerful productivity – Design Tools for Power and Clock Management

Related Products

A perfect fit – PAC-Designer is custom tailored for designing with Power Manager and Platform Manager devices.

Get going, get done – PAC-Designer is the complete implementation and verification solution for Power Manager and Platform Manager devices.

Works well with others – Works seamlessly with Lattice Diamond software to let you easily develop innovative mixed signal solutions.

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Overview

Lattice sets the industry standard for integrated power, platform and clock management devices, and PAC-Designer design software is the key that unlocks the potential of these solutions for your design.

Move to a More Productive Environment

  • Fully integrated design and simulation environment for Platform Manager, Power Manager II, and ispClock devices
  • High level logic design mechanism
  • Easy-to-use GUI
  • For Platform Manager, PAC-Designer works in conjunction with ispLEVER to form a complete CPLD/FPGA design environment

Trust, but Verify

  • Export VHDL or Verilog HDL models to popular 3rd party HDL simulators
  • Create your power management stimulus graphically
  • Digital waveform simulation for easy design verification
  • Simulate power supply rate

Painless Programming

  • Use Diamond Programmer (included in Lattice Diamond) to download your designs to silicon for Platform Manager
  • For products other than Platform Manager, PAC-Designer can be used directly to program Platform Manager, Power Manager II and ispClock devices

Licensing

PAC-Designer License (only required for PAC-Designer 5.1 or earlier)

To request a license you will need the following:

  • Lattice website user account
  • Hard drive serial number

Click here to request your license.

Software Downloads & Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
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Fail-Safe Sequencing During Field Upgrades Source Files
DT60881.26/6/2012ZIP591.5 KB
Fail-Safe Sequencing During Field Upgrades with Platform Manager
AN608801.26/6/2012PDF1.1 MB
ispPAC-POWR1220AT8 I2C Hardware Verification Utility
AN606701.011/21/2005PDF563.7 KB
Optimizing the Accuracy of ispPAC Power Manager Timers
AN607601.012/12/2007PDF215.9 KB
Powering Up and Programming the ispPAC-POWR607
AN607801.14/21/2011PDF1.3 MB
Scalable Centralized Power Management Source Files
DT60891.26/6/2012ZIP520.7 KB
Scalable Centralized Power Management with Field Upgrade Support
AN608901.26/6/2012PDF1.1 MB
Using ispVM System to Program ispPAC Devices
AN606201.05/1/2004PDF709.2 KB
Using PAC-Designer's Power Manager Waveform Editor
AN605401.011/23/2005PDF276.3 KB
Using the HVOUT Simulator Utility to Estimate FET Ramp Times
AN607001.011/21/2005PDF540.1 KB
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Fail-Safe Sequencing During Field Upgrades Source Files
DT60881.26/6/2012ZIP591.5 KB
Fail-Safe Sequencing During Field Upgrades with Platform Manager
AN608801.26/6/2012PDF1.1 MB
ispPAC-POWR1220AT8 I2C Hardware Verification Utility
AN606701.011/21/2005PDF563.7 KB
Optimizing the Accuracy of ispPAC Power Manager Timers
AN607601.012/12/2007PDF215.9 KB
Powering Up and Programming the ispPAC-POWR607
AN607801.14/21/2011PDF1.3 MB
Scalable Centralized Power Management Source Files
DT60891.26/6/2012ZIP520.7 KB
Scalable Centralized Power Management with Field Upgrade Support
AN608901.26/6/2012PDF1.1 MB
Using ispVM System to Program ispPAC Devices
AN606201.05/1/2004PDF709.2 KB
Using PAC-Designer's Power Manager Waveform Editor
AN605401.011/23/2005PDF276.3 KB
Using the HVOUT Simulator Utility to Estimate FET Ramp Times
AN607001.011/21/2005PDF540.1 KB
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PAC-Designer Installation Notice 6.32
6.322/22/2016PDF387.3 KB
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PAC-Designer Software User Manual 6.32
1.06/1/2014PDF3.3 MB
Platform Designer 3.11 User Guide
1.06/1/2019PDF697.9 KB
Platform Management Utility Functions IP Core User's Guide
IPUG9401.11/24/2011PDF551.8 KB
Platform Manager Development Kit User's Guide
EB5801.212/7/2010PDF1.6 MB
Power Manager II Hercules Development Kit User's Guide
EB5701.012/22/2010PDF3 MB
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BSCAN1 - Multiple Boundary Scan Port Addressable Buffer - Documentation
FPGA-RD-021057.41/29/2021PDF993.7 KB
BSCAN1 - Multiple Boundary Scan Port Addressable Buffer - Source Code
RD10017.34/18/2011ZIP152.4 KB
BSCAN2 - Multiple Boundary Scan Port Linker - Source Code
RD10024.63/13/2014ZIP2.6 MB
BSCAN2 - Multiple Scan Port Linker - Documentation
FPGA-RD-021064.91/29/2021PDF918.1 KB
Closed Loop Power Supply Trimming Documentation
RD10781.012/6/2010PDF278.2 KB
Closed Loop Power Supply Trimming Source Code
RD10781.012/6/2010ZIP269.4 KB
Error Logging Using Platform Manager Documentation
RD10771.09/28/2010PDF422.5 KB
Error Logging Using Platform Manager Source Files
RD10771.09/28/2010ZIP372.9 KB
GPIO Expander, Documentation
RD10651.34/12/2011PDF280.6 KB
GPIO Expander, Source Code
RD10651.34/12/2011ZIP195.5 KB
Hercules Development Kit Demonstration Source Code
1.06/11/2010ZIP201.6 KB
I2C (Inter-Integrated Circuit) Master Controller - Documentation
RD10055.83/6/2014PDF987.4 KB
I2C (Inter-Integrated Circuit) Master Controller - Source Code
RD10055.91/10/2015ZIP809.7 KB
I2C (Inter-Integrated Circuit) Slave/Peripheral - Documentation
RD10541.612/1/2014PDF801.5 KB
I2C (Inter-Integrated Circuit) Slave/Peripheral - Source Code
RD10541.612/12/2014ZIP764.8 KB
I2C Slave to SPI Master Bridge - Documentation
FPGA-RD-021111.21/29/2021PDF863.9 KB
I2C Slave to SPI Master Bridge - Source Code
RD10941.112/23/2011ZIP180.4 KB
Long Delay Timers Using Platform Manager Documentation
RD10791.19/28/2010PDF874.1 KB
Long Delay Timers Using Platform Manager Source Files
RD10791.09/28/2010ZIP683.9 KB
Platform Manager Dev Kit Initial Demo Source Files
RD1.11/26/2011ZIP1.1 MB
Power Management Bus Reference Design - Source Code
RD11001.112/23/2011ZIP378.3 KB
Power Management Bus Reference Design Documentation
FPGA-RD-020971.21/22/2021PDF1.1 MB
PWM Fan Controller
RD10601.69/10/2014PDF481.5 KB
PWM Fan Controller - Source Code
RD10601.71/16/2015ZIP2.9 MB
Serial Peripheral Interface (SPI) - Documentation
RD10751.112/23/2011PDF158.7 KB
Serial Peripheral Interface (SPI) - Source Code
RD10751.112/23/2011ZIP124.8 KB
SPI GPIO Expander - Documentation
RD10731.112/23/2010PDF212.5 KB
SPI GPIO Expander - Source Code
RD10731.112/23/2010ZIP161.6 KB
Temperature Monitor Using Platform Manager Documentation
RD10801.09/28/2010PDF330 KB
Temperature Monitor Using Platform Manager Source Files
RD10801.09/28/2010ZIP256.7 KB
UART (Universal Asynchronous Receiver/Transmitter) - Source Code
7/15/2025ZIP772.5 KB
UART (Universal Asynchronous Receiver/Transmitter) - User Guide
FPGA-RD-022701.87/15/2025PDF741.9 KB
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Platform Manager Product Brochure
I02081.04/10/2012PDF2.8 MB
Platform Manager Product Brochure (Chinese)
I0208C1.06/4/2012PDF2.9 MB
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Software Cable Support
2.07/16/2012PDF194.8 KB
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PAC-Designer Tutorial: Designing Power Manager II
This tutorial shows you how to use several processes, tools, and reports of the PAC-Designer software suite to program digital and analog elements of the ispPAC®-POWR1220AT8 device.		PDT0101.18/15/2008PDF1.3 MB
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LPTM10_12107_XO640
1.0110/8/2014BSM30.3 KB
LPTM10_1247_MO640
1.0110/8/2014BSM24.9 KB
Platform Manager 128 TQFP BSDL Files
1.12/26/2013ZIP8.4 KB
Platform Manager 208 ftBGA BSDL Files
1.12/27/2014ZIP10 KB
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PAC Designer 6.30 for Windows
6.329/26/2023ZIP120.1 MB
Selecting Power and Platform Manager Devices Excel Spreadsheet Tool
1.13/19/2012ZIP63.1 KB

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