ispClock

IF (time = money), THEN (use ispClock)

Time waits for no silicon – Why waste time with zero-delay buffers, fan-out buffers, termination resistors, delay lines and serpentine clock trace layouts when ispClock devices can replace them all?

Even a stopped clock tells the right time twice a day – ispClock devices can be programmed in-system to generate multiple clock frequencies and drive clock nets with different signalling requirements.

Time stream compensation – Compensate for output differences in clock trace lengths, precisely match trace impedances and drive clock nets with different signalling requirements – all while meeting stringent skew and jitter standards.

Features

  • Available in multiple formats: ispClock5600A for clock generation, ispClock5400D for differential clock distribution and ispClock5300S for single-ended clock distribution
  • Reduce board space – a single ispClock replaces multiple types of clock devices
  • Maximum cycle-cycle jitter 70 ps (peak-peak)
  • Maximum phase jitter 50 ps
  • Support multiple interface types including: LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, Diff. SSTL, Diff. HSTL

Jump to

Family Table

ispClock Product Family Selector Guide

Feature ispClock5600A Family ispClock5400D Family ispClock5300S Family
Outputs 20 or 10 10 or 6 20, 16, 12, 8, or 4
Input Operating Frequency Range 8 to 400MHz 50 TO 400MHz 8 to 267MHz
Output Operating Frequency Range 4 to 400MHz 50 TO 400MHz 5 to 267MHz
VCO Operation 320 to 800MHz 400 TO 800MHz 160 to 400MHz
Spread Spectrum Compatibility Yes Yes Yes
Single-Ended Fan-out Buffer Interfaces LVTTL, LVCMOS, HSTL, eHSTL, SSTL None LVTTL, LVCMOS, HSTL, eHSTL, SSTL
Single-Ended Clock Reference and Feedback Interfaces LVTTL, LVCMOS, SSTL, HSTL LVCMOS LVTTL, LVCMOS, HSTL, eHSTL, SSTL
Differential Fan-out Buffer Interfaces SSTL, HSTL, LVDS, LVPECL LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS None
Differential Clock Reference and Feedback Interfaces HSTL, SSTL, LVDS, LVPECL LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS LVDS, LVPECL, HSTL, SSTL
Type of PLL Feedback Internal/External Internal/External External
M, N Dividers Count from 1 to 40 None None
Number of V Dividers 5 4 3
V Divider Count Range 2 to 80 (in steps of 2) 2 to 16 (in powers of 2) 1 to 32 (in powers of 2)
Maximum Cycle-Cycle Jitter 70ps (peak-peak) 29ps (peak-peak) 70ps (peak-peak)
Maximum Period Jitter (RMS) 12ps 2.5ps 12ps
Maximum Phase Jitter (RMS) 50ps 6ps Typ. 50ps
Maximum Static Phase Offset -100ps to 200ps -5ps to 95ps -40ps to 100ps
Frequencies Generated 5 4 3
Programmable Phase Skew 156ps to 12ns 156ps to 12ns 156ps to 5ns
Programmable Time Skew None 0ps to 288ps None
Fan-out Buffer Mode No Yes Yes
Programmable Termination 40 to 70Ω & 20Ω Setting None 40 to 70Ω & 20Ω Setting

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Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
Driving SERDES Reference Clocks with the ispClock5400D Differential Clock Buffer
AN608101.010/6/2009PDF741.8 KB
Interfacing ispClock5600A with Reference Clock Oscillators
AN607901.08/6/2008PDF513.5 KB
ispClock5620 Evaluation Board ispPAC-CLK5620-EV1
AN606411/1/2004PDF1019.1 KB
ispClock5620A Evaluation Board: ispPAC-CLK5620A-EV1
Describes the features and operation of the ispPAC-CLK5620A-EV1 evaluation board.
AN60723/1/2007PDF929.7 KB
Lattice OrCAD Capture Schematic Library
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
FPGA-SC-020059.012/16/2025ZIP3.2 MB
Using a Low-Cost CMOS Oscillator as a Reference Clock for SERDES Applications
AN608001.12/13/2012PDF202.4 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

TITLENUMBERVERSIONDATEFORMATSIZE
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ispClock 5600 Family Data Sheet Revision History
2/1/2005PDF8 KB
ispClock 5600A Family Data Sheet
DS101901.46/3/2008PDF969.3 KB
ispClock5300S Data Sheet
DS101001.410/1/2007PDF1.2 MB
ispClock5400D Family Data Sheet
DS102501.312/14/2011PDF1.6 MB
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
Driving SERDES Reference Clocks with the ispClock5400D Differential Clock Buffer
AN608101.010/6/2009PDF741.8 KB
Interfacing ispClock5600A with Reference Clock Oscillators
AN607901.08/6/2008PDF513.5 KB
ispClock5620 Evaluation Board ispPAC-CLK5620-EV1
AN606411/1/2004PDF1019.1 KB
ispClock5620A Evaluation Board: ispPAC-CLK5620A-EV1
Describes the features and operation of the ispPAC-CLK5620A-EV1 evaluation board.
AN60723/1/2007PDF929.7 KB
Using a Low-Cost CMOS Oscillator as a Reference Clock for SERDES Applications
AN608001.12/13/2012PDF202.4 KB
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
Generating a Single-Ended Clock Source from ispClock5400D Differential Clock Buffers - Source Code
RD10691.01/22/2010ZIP129.9 KB
Generating a Single-Ended Clock Source from ispClock5400D Differential Clock Buffers Reference Design - Documentation
RD10691.01/22/2010PDF171.3 KB
TITLENUMBERVERSIONDATEFORMATSIZE
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ACN03D-11 Withdrawal of ACN03C-11
Material Set
ANC03D-1114/1/2011PDF796.6 KB
PCN 02A-15 Affected_OPN_Listing
Discontinuance
3.08/12/2015XLSX310.4 KB
PCN 02A-15 SnPb and Select Mature Family Discontinuance
1.06/18/2015PDF316.9 KB
PCN02A-15 Frequently Asked Questions
2.06/18/2015DOCX60.8 KB
PCN06A-19 Mature Select Devices Discontinuance
6/25/2019PDF305.2 KB
PCN06C-11 Withdrawal of PCN06B-11
Material Set
PCN06C-111.08/1/2011PDF838.5 KB
PCN07B-19 Unisem Shutdown
PCN07B-1911/26/2019PDF348.2 KB
TITLENUMBERVERSIONDATEFORMATSIZE
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Lattice OrCAD Capture Schematic Library
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
FPGA-SC-020059.012/16/2025ZIP3.2 MB
TITLENUMBERVERSIONDATEFORMATSIZE
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ispClock Product Brief
I01686.012/5/2007PDF611.2 KB
ispClock Product Brief For Rebranding
I01688/16/2013PDF265 KB
ispClock5300S Product Brief
I01931.010/31/2012PDF1.1 MB
ispClock5400D Product Brief
I02001.011/1/2012PDF544.5 KB
Lattice FPGA Product Selector Guide
v25.3.01/6/2026PDF717 KB
Power Manager II and ispClock Application Examples
I01912.08/1/2007PDF456.1 KB
TITLENUMBERVERSIONDATEFORMATSIZE
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32 QFNS Pb-Free Device Material Content
Includes all 3 versions
D4/19/2016PDF51.1 KB
Lattice ispCLOCK Product Family Qualification Summary
A7/1/2009PDF383.3 KB
SN_SG48
Rev C19/20/2019PDF52.9 KB
SN64_PAC
Rev C4/19/2018PDF22 KB
TN_VN48 (PAC, M4A)
Rev B2/7/2018PDF25.3 KB
TN64_PAC
Rev D2/7/2018PDF23.1 KB
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Dynamic Power Management in an Embedded System
4/1/2005PDF619.6 KB
TITLENUMBERVERSIONDATEFORMATSIZE
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[BSDL ISC] ispCLOCK5304S 48 Pin TQFP
1.003/1/2007BSM15.4 KB
[BSDL ISC] ispCLOCK5308S 48 Pin TQFP
1.003/1/2007BSM15.4 KB
[BSDL ISC] ispCLOCK5312S 48 Pin TQFP
1.003/1/2007BSM15.7 KB
[BSDL ISC] ispCLOCK5316S 64 Pin TQFP
1.003/1/2007BSM17.2 KB
[BSDL ISC] ispCLOCK5320S 64 Pin TQFP
1.003/1/2007BSM17.4 KB
[BSDL ISC] ispCLOCK5510v 48 Pin TQFP
1.004/1/2005BSM17.8 KB
[BSDL ISC] ispCLOCK5520v 100 Pin TQFP
1.004/1/2005BSM19.1 KB
[BSDL ISC] ispCLOCK5610Av 48 Pin TQFP
1.014/21/2006BSM18.4 KB
[BSDL ISC] ispCLOCK5610v 48 Pin TQFP
1.016/1/2005BSM18.1 KB
[BSDL ISC] ispCLOCK5620Av 100 Pin TQFP
1.014/21/2006BSM20.1 KB
[BSDL ISC] ispCLOCK5620v 100 Pin TQFP
1.026/1/2005BSM19.8 KB
[BSDL] ispCLOCK5304S 48 Pin TQFP
1.003/1/2007BSM10 KB
[BSDL] ispCLOCK5308S 48 Pin TQFP
1.003/1/2007BSM10.3 KB
[BSDL] ispCLOCK5312S 48 Pin TQFP
1.003/1/2007BSM10.6 KB
[BSDL] ispCLOCK5316S 64 Pin TQFP
1.003/1/2007BSM12.3 KB
[BSDL] ispCLOCK5320S 64 Pin TQFP
1.003/1/2007BSM12.2 KB
[BSDL] ispCLOCK5406D 48 Pin TQFP
1.001/1/2009BSM12.3 KB
[BSDL] ispCLOCK5410D 64 Pin TQFP
1.001/1/2009BSM13 KB
[BSDL] ispCLOCK5510v 48 Pin TQFP
1.024/1/2005BSM13.4 KB
[BSDL] ispCLOCK5520v 100 Pin TQFP
1.024/1/2005BSM14.7 KB
[BSDL] ispCLOCK5610Av 48 Pin TQFP
1.014/21/2006BSM13.3 KB
[BSDL] ispCLOCK5610v 48 Pin TQFP
1.016/1/2005BSM13.2 KB
[BSDL] ispCLOCK5620Av 100 Pin TQFP
1.014/21/2006BSM15 KB
[BSDL] ispCLOCK5620v 100 Pin TQFP
1.016/1/2005BSM15.2 KB

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