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CertusPro-NX

Advanced General Purpose FPGA

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10G SERDES at Lowest Power and Smallest Package – Up to 8 SERDES lanes supporting up to 10.3 Gbps per lane, in packages as small as 9x9 mm. Up to 4x lower power vs. similar FPGAs.

More On-chip Memory, and LPDDR4 Support – Up to 7.3 Mb of on-chip memory. Only FPGA in class with LPDDR4 support. LPDDR4, DDR3/3L, LPDDR2 supported at 1066 Mbps.

Built on Lattice Nexus platform – Class-leading power efficiency. Up to 100x higher reliability, due to 100x lower Soft Error Rate (SER) from 28 nm FD-SOI technology.

Additional general purpose FPGA densities available in the Certus-NX Family.

CertusPro-NX

Features

  • Up to 100K logic cells, 7.3 Mb of embedded memory blocks (EBR, LRAM), 156 18 x 18 multipliers, 299 programmable I/O, 8 SERDES supporting up to 10.3 Gbps per lane and supporting popular protocols (10 Gig Ethernet, PCIe Gen 3, DisplayPort, SLVS-EC and CoaXPress).
  • Packages as small as 9x9 mm, and in ball-pitch options of 0.5, 0.8 and 1.0 mm.
  • Power modes – User selectable Low Power vs. High Performance modes, enabled by FD-SOI programmable back-bias.
  • Design security – ECDSA bitstream authentication, coupled with robust AES-256 encryption.
  • Fast configuration – I/O configures in 4 ms, and full-device in under 30 ms in 100K LC device.
  • Available in Commercial, Industrial and Automotive (AEC-Q100 qualified) temperature grades.

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CertusPro-NX Device Selection Guide
Additional general purpose FPGA densities in Certus-NX Family
Features LFCPNX-50 LFCPNX-100
Logic Cells 52K 96K
Embedded Memory (EBR) Bits (Kb) 1728
 3744
Large Memory (LRAM) Bits (Kb) 2048
 3584
18 X 18 Multipliers 96
 156
ADC Blocks 2
 2
GPLL 3
 4
PCIe Gen3 Hard IP 1
 1
Temperature Grades1 C, I, A C, I, A
0.5 mm Total I/O (Wide Range, High Performance, ADC3) / SERDES Lanes

LFCPNX-50 LFCPNX-100
ASG256 (9 x 9 mm)2 165 (75, 84, 6) / 4
 165 (75, 84, 6) / 4
0.8 mm Total I/O (Wide Range, High Performance, ADC3) / SERDES Lanes

LFCPNX-50 LFCPNX-100
CBG256 (14 x 14 mm)2 165 (75, 84, 6) / 4
 165 (75, 84, 6) / 4
BBG484 (19 x 19 mm)2 269 (167, 96, 6) / 4
 305 (167, 132, 6) / 8
1.0 mm Total I/O (Wide Range, High Performance, ADC3) / SERDES Lanes

LFCPNX-50 LFCPNX-100
BFG484 (23 x 23 mm) 269 (167, 96, 6) / 4
305 (167, 132, 6) / 4
LFG672 (27 x 27 mm) — 305 (167, 132, 6) / 8

1. C = Commercial, I = Industrial, A = Automotive
2. Available in Automotive Grade
3. Each ADC pin count reflects using dedicated complement pair and vRef

Example Solutions

Smart SFP+ Optical ModuleExpand Image

Smart SFP+ Optical Module

  • Implement enhanced Ethernet functions (e.g., Ethernet demarcation, OAM processing, SLA monitoring, etc.)
  • Compact packages as small as 9x9 mm with 10 Gigabit Ethernet support and 100K Logic Cells
  • Class-leading power efficiency for simpler thermal management
  • Hardened 10 Gigabit Ethernet PCS blocks supporting 10GBASE-R at 10.3125 Gbps, and available Ethernet MAC IP
Control Plane Security and Hardware ManagementExpand Image

Control Plane Security and Hardware Management

  • Bridge CPU via PCIe to multiple control plane peripherals (I2C, UART, GPIO), board management functions, and 10GE control plane traffic
  • Security functions (e.g., encryption, authentication) implemented in FPGA helps secure control plane traffic
  • 10G SERDES supporting PCIe Gen 3 x4 (in hard IP) and 10 Gigabit Ethernet (with 10GBASE-R PCS in hard IP)
  • High system reliability and up-time due to 100x lower Soft Error Rate (SER) from FD-SOI technology
  • Fast FPGA configuration supports board management needs and PCIe boot-time requirements
Machine Vision BDExpand Image

Machine Vision

  • Vision processing and bridging for high performance SLVS-EC sensors
  • 10G SERDES supporting SLVS-EC sensor interface, 10 GigE Vision and CoaXPress
  • 9x9 mm small size package and class-leading power efficiency meets stringent requirements of space and thermal budget constrained camera modules
  • Up to 7.3 Mb on-chip memory for ISP and vision processing
  • LPDDR4 external memory support for optional frame buffering
Frame Grabber BDExpand Image

Frame Grabber

  • Image acquisition, pre-processing and DMA over PCIe to host PC
  • 10G SERDES supporting 10 GigE Vision, CoaXPress and PCIe Gen 3 x4 (in hard IP)
  • Up to 7.3 Mb on-chip memory for video processing / tagging
  • LPDDR4 external memory support for optional frame buffering
Smart Camera AI ProcessingExpand Image

Smart Camera AI Processing

  • Offload AI processing and ISP from SoC
  • Interface with popular image sensors over MIPI at up to 1.5 Gbps per lane, using High Performance IO (HPIO)
  • Up to 7.3 Mb on-chip memory and flexible DSP resources to efficiently perform AI processing and ISP
  • LPDDR4 external memory support for frame buffering
  • Flexible output over MIPI or PCIe to SoC to enable smart device with high quality imaging

Videos

Lattice Automate™ Stack V4.0
Expand Video

Lattice Automate™ Stack V4.0

Lattice demonstates the Lattice Automate solution stack that provides Industrial automation system designers with tools needed to evaluate, develop, and deploy FPGA-based, RISC-V software programmable applications.
CAST TSN Endpoint
Expand Video

CAST TSN Endpoint

This demo features a TSN Ethernet endpoint reference design on the Lattice CertusPro™-NX platform, suitable for industrial automation, automotive, and other applications. The TSN endpoint supports timing synchronization (IEEE 802.1AS), traffic shaping (802.1Qav/Qbv) with pre-emption support (802.1Qbu and 802.3br), and optional redundancy (802.1CB).
E-Con Systems Multi-Camera Frame Grabber Card
Expand Video

E-Con Systems Multi-Camera Frame Grabber Card

This demo showcases a robust automotive multi-camera system, featuring a frame grabber card that aggregates video inputs from eight STURDeCAM31 cameras via GMSL and transmits the output to the host through PCI.
El Camino Industrial Control Reference Design Using Ethernet-Based Fieldbus Standards for Remote I/O Communication
Expand Video

El Camino Industrial Control Reference Design Using Ethernet-Based Fieldbus Standards for Remote I/O Communication

This demo showcases quick evaluation and rapid prototyping with the new Lattice ADI Board. It is ready for PROFINET and EtherCAT industrial communication, supporting remote I/O real-time communication for industrial control solutions utilizing the IEEE Ethernet standard and dedicated industrial protocols. Featuring a PROFINET solution based on the Lattice reference design, this demo provides insights into the operation of various industrial protocols.
intoPIX RAW Bayer Compressed Video Data Transported Over Ethernet Using TicoRAW
Expand Video

intoPIX RAW Bayer Compressed Video Data Transported Over Ethernet Using TicoRAW

Discover how integrating TicoRAW technology into the Holoscan SDK reference design revolutionizes video data transfer. This demo showcases the seamless compression and transmission of RAW Bayer video data over Ethernet, highlighting the efficiency and quality preservation of TicoRAW.
Logic Fruit Technologies Inc. ARINC 818-3 IP
Expand Video

Logic Fruit Technologies Inc. ARINC 818-3 IP

Logic Fruit Technologies designed and implemented the ARINC 818-3 transmitter and receiver IP core to support multiple line rates up to 24x. This IP core adheres to the DO-254 methodology and boasts a DAL-B certification. In this demo, we have successfully ported our IP onto the Lattice CertusPro™-NX FPGA, showcasing its robust performance and versatility.
Macnica Practical Design for Customers Using Lattice PCIe IP
Expand Video

Macnica Practical Design for Customers Using Lattice PCIe IP

Introducing the PCIe Rapid Start Project: Developed by Macnica for Lattice users unfamiliar with PCIe, this project utilizes minimal resources while meeting the needs of the industrial market with its Gen 2 x 1 design. Key features include interrupt support, sufficient timing margin, and practical DMA control, known as “Smart DMA.” This package is designed to facilitate the adoption of Lattice devices and expedite development for customers.
Neurala DNN Acceleration with Lattice CertusPro™-NX
Expand Video

Neurala DNN Acceleration with Lattice CertusPro™-NX

This demo showcases the use of Neurala’s patented L-DNN technology, where AI model processing is efficiently shared between a Lattice FPGA and a Raspberry Pi (RasPi). The neural network (NN) backbone is processed on the Lattice CertusPro™-NX, while the NN head runs on the companion chip (RasPi). This setup demonstrates the seamless integration and collaborative processing capabilities of Lattice FPGAs and RasPi, highlighting their potential in advanced AI applications.
Oregano Systems 10 Gbit High-Accuracy PTP Solution
Expand Video

Oregano Systems 10 Gbit High-Accuracy PTP Solution

This latest addition to the syn1588 product family is a low-power, high-accuracy PTP-enabled 10Gbit Ethernet network interface card, utilizing Oregano Systems’ sophisticated PTP IP cores. Based on the Lattice CertusPro™-NX device, this demo will showcase its interaction with a high-performance 10Gbit PTP Grandmaster from Meinberg Funkuhren.
Sensor Fusion - Radar, Lidar, Camera + Robot Arm Control
Expand Video

Sensor Fusion - Radar, Lidar, Camera + Robot Arm Control

This demo processes radar, LiDAR, and camera sensors simultaneously, showcasing the fused data processing among the sensors in real time. It demonstrates the flexibility of I/O and the computing power to handle multiple sensors and machine learning (ML). Sensor data (camera, radar, pressure) is pre-processed by the FPGA and sent to the CPU (Raspberry Pi) over PCIe. The CPU controls the robot arm and sends position info back to the FPGA, which generates commands for the arm.
Server Management Application with Lattice OpenBIC Solution
Expand Video

Server Management Application with Lattice OpenBIC Solution

The demo showcases the Open Baseboard Interface Controller solution with Meta YB3 server solution, The Lattice FPGA collects all sensor information and passes the information to BMC.
Tecphos GigEVision and CoaXPress IP for Lattice CertusPro™-NX
Expand Video

Tecphos GigEVision and CoaXPress IP for Lattice CertusPro™-NX

This demo showcases the Lattice CertusPro™-NX FPGA receiving a video stream over coax from an off-the-shelf CoaXPress camera and delivering that video stream over Ethernet to a standard PC, which will display the video stream on a monitor.
Lattice ORAN™ Radio Unit Implemented on CPNX-100
Expand Video

Lattice ORAN™ Radio Unit Implemented on CPNX-100

In this demo, we introduce the Lattice ORAN™ Radio Unit (O-RU), which features advanced capabilities such as Lower PHY baseband processing on the Lattice CertusPro™-NX FPGA. It includes FFT/IFFT, CP addition and removal, PRACH filtering, and digital beamforming. The O-RU supports up to 4 transmit and 4 receive antennas (4T4R), offers an RF bandwidth of 100MHz, and operates at frequencies up to 6GHz. Additionally, it has Ethernet interfaces for I&Q sample exchange with Higher PHY and a JESD204B interface with RFFE, highlighting its robust performance and versatility in modern communication systems.
CertusPro-NX: Power Consumption Comparison
Expand Video

CertusPro-NX: Power Consumption Comparison

See a competitive power consumption demo comparing the power consumption of a Lattice CertusPro-NX running a 10 Gbps SERDES design with two similar competing FPGAs.
CertusPro-NX: AI/ML Analytics Demonstration
Expand Video

CertusPro-NX: AI/ML Analytics Demonstration

This demonstration highlights the advanced smart vision analytics enabled by a Lattice CertusPro-NX FPGA’s high internal memory density and fast parallel processing architecture.
CertusPro-NX: Reliability Comparison
Expand Video

CertusPro-NX: Reliability Comparison

A leading cause of silicon malfunctions are single event upsets (SEUs) caused by radiation particle strikes. In this competitive demonstration, the reliability of Lattice CertusPro-NX FPGAs when exposed to a stream of alpha particles is compared with two similar competing devices.

Awards

2022 LEAP AwardExpand Image

Leadership in Engineering Achievement Program (LEAP) Awards 2022

Gold Medal - Embedded Computing Category

2022 EW Best in ShowExpand Image

Embedded Computing Design’s Embedded World Best in Show Award

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