Power Manager II

Integrated board power management functions for the forward thinking engineer

Power control, without the touch of a button – With Power Manager you can monitor and control up to 12 power supplies with unparalleled accuracy and speed, and respond to faults in <65 μs to protect on-board flash memory from corruption.

Reduce BOM costs– The easiest way to manage board-mounted power supplies – Power Manager II integrates hot-swap controllers, power supply OR’ing, sequencing, voltage monitoring, reset generation, trimming, margining, and more.

Design made simple – PAC-Designer software supports the Power Manager II family offering the convenience of design and verification of power sequencing and monitoring circuit using PC-based software – prior to uploading to the device.

Features

  • Up to 12 differential voltage sensors with immunity to noise on ground plane
  • Voltage trimming to within 1%
  • Ruggedized CPLD with up to 48 macrocells for sequencing and supervisory signal logic
  • Large operating power supply range (3.3 V + 20% to 3.3 V -15%)
  • Up to 4 High-Voltage MOSFET Driver Outputs
  • Voltage Measurement with 10-bit ADC through I2C
  • Up to 8 On-chip DACs for Margining and Trimming

Jump to

Family Table

Power Manager II Application Cross Reference Guide

  ProcessorPM POWR607 POWR1014 POWR1014A POWR1220AT8
Board input (Primary) Supply Management Hot-swap
-48V Hot-swap   Check Mark Check Mark Check Mark Check Mark
+12/24V Hot Swap   Check Mark Check Mark Check Mark Check Mark
Power Feed To External Systems
-48V Supply Feed   Check Mark Check Mark Check Mark Check Mark
+12/24V Supply Feed   Check Mark Check Mark Check Mark Check Mark
Redundant Supply Selection
-48V Supply O R'ing   Check Mark Check Mark Check Mark Check Mark
+12/24V Supply O R'ing   Check Mark Check Mark Check Mark Check Mark
Payload (Secondary) Power Management
Supply Sequencing   Check Mark Check Mark Check Mark Check Mark
Voltage Supervision Check Mark Check Mark Check Mark Check Mark Check Mark
Reset Generation Check Mark Check Mark Check Mark Check Mark Check Mark
Watchdog Timer Check Mark Check Mark Check Mark Check Mark Check Mark
Voltage Measurement Using ADC       Check Mark Check Mark
Power Supply Voltage Trimming         Check Mark
Power Supply Margining         Check Mark

Lattice Automotive (AEC-Q100 qualified) ispPAC-POWR1014/A Device Selection Guide

  LA-POWR1014 LA-POWR1014A
Analog Input Pins 10 10
Programmable Comparators 20 20
Trip Point per input 368 368
Lowest Supply Voltage Monitored 0.7V 0.7V
Power-off Detection 75mV 75mV
CPLD Macrocells 24 24
Outputs 14 14
FET Drivers 2 2
ADC Resolution - 10 Bits
I2C Support - Yes
Operating Voltage 2.8V to 3.9V 2.8V to 3.9V
Package 48-Pin TQFP 48-Pin TQFP

Design Resources

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Development Kits & Boards

Our development boards & kits help streamline your design process

Application Notes

Learn how to get the most from our line-up of FPGAs / development boards

Programming Hardware

Take the strain out of in-system programming & in-circuit reconfiguration with our programming hardware

Complete Design Flows, High Ease of Use

Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
Controlling and Monitoring Power-One Bricks and SIPs with Lattice Power Manager Devices
AN605601.14/17/2008PDF216.1 KB
Extending the VMON Input Range of Power/Platform Management Devices
FPGA-AN-020312.59/21/2021PDF1.1 MB
Fail-Safe Sequencing During Field Upgrades Source Files
DT60881.26/6/2012ZIP591.5 KB
Fail-Safe Sequencing During Field Upgrades with Platform Manager
AN608801.26/6/2012PDF1.1 MB
High-side Current Sensing Techniques for Power Manager Devices
AN604901.14/17/2008PDF70.9 KB
Implementing Power Supply Sequencers with Power/Platform Management Devices and PAC-Designer LogiBuilder
AN604201.210/7/2011PDF277 KB
Interfacing Power Manager Devices with Modular DC-to-DC Converters
AN604601.14/17/2008PDF494.6 KB
Interfacing the Trim Output of Power Manager II Devices to DC-DC Converters
AN60741.24/7/2015PDF3.1 MB
ispPAC-POWR1014/A Data Sheet
FPGA-DS-020892.311/20/2020PDF4.7 MB
ispPAC-POWR1220AT8 Evaluation Board
AN606501.23/1/2007PDF305.3 KB
ispPAC-POWR1220AT8 I2C Hardware Verification Utility
AN606701.011/21/2005PDF563.7 KB
Lattice OrCAD Capture Schematic Library
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
FPGA-SC-020059.012/16/2025ZIP3.2 MB
Monitoring and Controlling Negative Power Supplies with Power Manager Devices
AN605102.14/17/2008PDF67.9 KB
Optimizing the Accuracy of ispPAC Power Manager Timers
AN607601.012/12/2007PDF215.9 KB
Powering Up and Programming the ispPAC-POWR1014/A
AN607501.14/11/2011PDF190.4 KB
Powering Up and Programming the ispPAC-POWR1220AT8
AN607301.14/21/2011PDF171.2 KB
Powering Up and Programming the ispPAC-POWR607
AN607801.14/21/2011PDF1.3 MB
Powering Up and Programming the ProcessorPM ispPAC-POWR605
AN608201.14/21/2011PDF1.1 MB
Programmable Comparator Options for ispPAC-POWR1220AT8
AN606901.011/21/2005PDF259.4 KB
Programming the ispPAC-POWR1220AT8 in a JTAG Chain Using the ATDI Pin
AN606801.12/28/2011PDF245.8 KB
Scalable Centralized Power Management Source Files
DT60891.26/6/2012ZIP520.7 KB
Scalable Centralized Power Management with Field Upgrade Support
AN608901.26/6/2012PDF1.1 MB
Simulating Power Supply Sequences for Power Manager Devices Using PAC-Designer LogiBuilder
AN60441.14/17/2008PDF409.4 KB
Stable Operation of DC-DC Converters with Power Manager Closed Loop Trim
AN60771.110/8/2014PDF676.8 KB
Using ispVM System to Program ispPAC Devices
AN606201.05/1/2004PDF709.2 KB
Using PAC-Designer's Power Manager Waveform Editor
AN605401.011/23/2005PDF276.3 KB
Using Power MOSFETs with Power/Platform Management Devices
AN60481.38/29/2017PDF734.6 KB
Using the HVOUT Simulator Utility to Estimate FET Ramp Times
AN607001.011/21/2005PDF540.1 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

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ispPAC-POWR1014/A Data Sheet
FPGA-DS-020892.311/20/2020PDF4.7 MB
ispPAC-POWR1220AT8 Data Sheet
FPGA-DS-020512.04/11/2019PDF4.9 MB
ispPAC-POWR607 Data Sheet
DS10112.04/27/2015PDF2.7 MB
ispPAC-POWR6AT6 Data Sheet
DS10161.511/13/2013PDF3.2 MB
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
FPGA-DS-020901.410/26/2020PDF5.6 MB
ProcessorPM - POWR605 Data Sheet
DS10342.04/10/2015PDF2.7 MB
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
Controlling and Monitoring Power-One Bricks and SIPs with Lattice Power Manager Devices
AN605601.14/17/2008PDF216.1 KB
Extending the VMON Input Range of Power/Platform Management Devices
FPGA-AN-020312.59/21/2021PDF1.1 MB
Fail-Safe Sequencing During Field Upgrades Source Files
DT60881.26/6/2012ZIP591.5 KB
Fail-Safe Sequencing During Field Upgrades with Platform Manager
AN608801.26/6/2012PDF1.1 MB
High-side Current Sensing Techniques for Power Manager Devices
AN604901.14/17/2008PDF70.9 KB
Implementing Power Supply Sequencers with Power/Platform Management Devices and PAC-Designer LogiBuilder
AN604201.210/7/2011PDF277 KB
Interfacing Power Manager Devices with Modular DC-to-DC Converters
AN604601.14/17/2008PDF494.6 KB
Interfacing the Trim Output of Power Manager II Devices to DC-DC Converters
AN60741.24/7/2015PDF3.1 MB
ispPAC-POWR1220AT8 Evaluation Board
AN606501.23/1/2007PDF305.3 KB
ispPAC-POWR1220AT8 I2C Hardware Verification Utility
AN606701.011/21/2005PDF563.7 KB
Monitoring and Controlling Negative Power Supplies with Power Manager Devices
AN605102.14/17/2008PDF67.9 KB
Optimizing the Accuracy of ispPAC Power Manager Timers
AN607601.012/12/2007PDF215.9 KB
Powering Up and Programming the ispPAC-POWR1014/A
AN607501.14/11/2011PDF190.4 KB
Powering Up and Programming the ispPAC-POWR1220AT8
AN607301.14/21/2011PDF171.2 KB
Powering Up and Programming the ispPAC-POWR607
AN607801.14/21/2011PDF1.3 MB
Powering Up and Programming the ProcessorPM ispPAC-POWR605
AN608201.14/21/2011PDF1.1 MB
Programmable Comparator Options for ispPAC-POWR1220AT8
AN606901.011/21/2005PDF259.4 KB
Programming the ispPAC-POWR1220AT8 in a JTAG Chain Using the ATDI Pin
AN606801.12/28/2011PDF245.8 KB
Scalable Centralized Power Management Source Files
DT60891.26/6/2012ZIP520.7 KB
Scalable Centralized Power Management with Field Upgrade Support
AN608901.26/6/2012PDF1.1 MB
Simulating Power Supply Sequences for Power Manager Devices Using PAC-Designer LogiBuilder
AN60441.14/17/2008PDF409.4 KB
Stable Operation of DC-DC Converters with Power Manager Closed Loop Trim
AN60771.110/8/2014PDF676.8 KB
Using ispVM System to Program ispPAC Devices
AN606201.05/1/2004PDF709.2 KB
Using PAC-Designer's Power Manager Waveform Editor
AN605401.011/23/2005PDF276.3 KB
Using Power MOSFETs with Power/Platform Management Devices
AN60481.38/29/2017PDF734.6 KB
Using the ABEL Tools of PAC-Designer with Power Manager Devices
AN605202.05/1/2003PDF777 KB
Using the HVOUT Simulator Utility to Estimate FET Ramp Times
AN607001.011/21/2005PDF540.1 KB
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ispPAC-POWR607 Evaluation Board User's Guide
Describes the features and functions of the ispPAC-POWR607 Evaluation Board
5/23/2007PDF1.2 MB
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12V Hot Swap Control - Documentation
RD10681.04/26/2010PDF469.8 KB
12V Hot Swap Control - Source Code
RD10681.04/26/2010ZIP371.1 KB
5V and 3.3V Hot Swap Controller - Documentation
RD10571.08/4/2009PDF185.3 KB
5V and 3.3V Hot Swap Controller - Source Code
RD10571.08/6/2009ZIP135 KB
AMC Module Power Management - Documentation
RD10701.04/26/2010PDF532.3 KB
AMC Module Power Management - Source Code
RD10701.04/26/2010ZIP468.3 KB
Hercules Development Kit Demonstration Source Code
1.06/11/2010ZIP201.6 KB
OrCAD Capture (.dsn) format schematics
19/28/2010ZIP0.7 KB
Redundant Power Supply Management
RD10641.04/26/2010PDF508.9 KB
Redundant Power Supply Management - Source Code
RD10641.04/26/2010ZIP441.3 KB
Supervisor, WDT and Reset Generation with ProcessorPM - Documentation
RD10561.08/17/2009PDF815.7 KB
Supervisor, WDT and Reset Generation with ProcessorPM - Source Code
RD10561.08/3/2009ZIP744.4 KB
Voltage Monitoring for Fault Logging - Documentation
RD10721.04/26/2010PDF447.5 KB
Voltage Monitoring for Fault Logging - Source Code
RD10721.04/26/2010ZIP327.3 KB
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ACN03D-11 Withdrawal of ACN03C-11
Material Set
ANC03D-1114/1/2011PDF796.6 KB
PCN06C-11 Withdrawal of PCN06B-11
Material Set
PCN06C-111.08/1/2011PDF838.5 KB
PCN07B-19 Unisem Shutdown
PCN07B-1911/26/2019PDF348.2 KB
PCN13A-10 Notification of intent to discontinue select mature devices
PCN13A-1019/7/2010PDF163.7 KB
PCN13A-10 Notification of intent to discontinue select mature devices - Japanese Language
PCN13A-1019/7/2010PDF205.1 KB
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
Lattice OrCAD Capture Schematic Library
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
FPGA-SC-020059.012/16/2025ZIP3.2 MB
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Automotive Solutions Product Brief
I01648.06/5/2009PDF2.4 MB
Lattice FPGA Product Selector Guide
v25.3.01/6/2026PDF717 KB
Power Failure Protection for Solid State Drives
Illustrates several power management improvements for SSD that improve reliablity while lowering system costs.
I02271.06/7/2012PDF864.3 KB
Power Manager II and ispClock Application Examples
I01912.08/1/2007PDF456.1 KB
Power Manager II Product Brief
I01787.08/14/2013PDF1.7 MB
Power Manager II Product Brief (Chinese)
I0178C6.011/13/2012PDF2.1 MB
ProcessorPM - POWR605 Product Brochure
I02011.04/24/2009PDF1.6 MB
ProcessorPM Development Kit Product Brief
I02021.05/22/2013PDF673.4 KB
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32 QFNS Pb-Free Device Material Content
Includes all 3 versions
D4/19/2016PDF51.1 KB
Lattice ispPAC-POWR Product Family Qualification Summary
J1/22/2021PDF493 KB
SN_SG32
Rev I5/1/2024PDF145.6 KB
SN24_PAC
Rev F2/7/2018PDF22.1 KB
TN_VN100_4k_M4A_PAC
Rev B110/13/2021PDF124.1 KB
TN_VN48 (PAC, M4A)
Rev B2/7/2018PDF25.3 KB
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PAC-Designer Tutorial: Designing Power Manager II
This tutorial shows you how to use several processes, tools, and reports of the PAC-Designer software suite to program digital and analog elements of the ispPAC®-POWR1220AT8 device.
PDT0101.18/15/2008PDF1.3 MB
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Complex Power Management: An Imperative for Modern System Design
11/1/2005PDF220.6 KB
Distributed PLD Solution for Reduced Server Cost and Increases Flexibility
WP0091.08/1/2017PDF708.1 KB
Dynamic Power Management in an Embedded System
4/1/2005PDF619.6 KB
Load Switching Helps Implement Hot Swaping
1.03/1/2010PDF215.9 KB
Managing Power Sequencing for the LatticeSC FPGA
2/1/2007PDF312.9 KB
Power Management for Computer Peripherals - White Paper (Chinese Language Version)
1.05/31/2012PDF262.8 KB
Reset Generation for TI DSP Processor
1.03/1/2010PDF64.9 KB
Reset Generation for TI DSP Processor (Chinese Language)
1.06/28/2010PDF226.5 KB
Reset Generation for TI DSP Processor (Japanese Language)
1.03/1/2010PDF156.6 KB
Reset Generation for TI DSP Processor (Korean Language)
5/22/2013PDF321.1 KB
Reset Generation for TI DSP Processor (Traditional Chinese Language)
1.06/28/2010PDF286 KB
Transforming Circuit Board Design
1.09/26/2011PDF424.3 KB
Transforming Circuit Board Design (Chinese Language)
1.09/26/2011PDF449.1 KB
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[BSDL] ispPAC-POWR1014 48-pin TQFP
1.004/11/2006BSM8.2 KB
[BSDL] ispPAC-POWR1014A 48-pin TQFP
1.004/1/2006BSM7.8 KB
[BSDL] ispPAC-POWR1220AT8 100-pin TQFP
1.025/24/2006BSM12.9 KB
[BSDL] ispPAC-POWR605 24-pin QFNS
1.04/27/2009BSM8.1 KB
[BSDL] ispPAC-POWR607 24-pin QFN
1.08/1/2014BSM7.4 KB
[BSDL] ispPAC-POWR607 32-pin QFN
1.02/1/2007BSM7.5 KB
[BSDL] ispPAC-POWR6AT6 32-pin QFN
1.02/1/2007BSM7.9 KB
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[IBIS] ispPAC-POWR1014/1014A
0.12/1/2007IBS276.6 KB
[IBIS] ispPAC-POWR1220AT8
0.23/2/2012IBS412.3 KB
[IBIS] ispPAC-POWR605
0.17/1/2009IBS174.8 KB
[IBIS] ispPAC-POWR607
0.12/1/2007IBS224.6 KB
[IBIS] ispPAC-POWR6AT6
0.12/1/2007IBS145.2 KB
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POWR1014A Breakout Board Demo Source
This demo includes the PAC-Designer project source for the preprogrammed demonstration design. It programs the POWR1014A with power supply enable sequence logic and a counter circuit using the embedded timer & open-drain digital pins configured for LED
1.03/21/2011ZIP7.4 KB
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Selecting Power and Platform Manager Devices Excel Spreadsheet Tool
1.13/19/2012ZIP63.1 KB

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