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Certus-NX

Low-Power General Purpose FPGA

Related Products

Related Applications

Industry-leading I/O Count in Small Packages – Up to 2x more I/O per mm2 vs. similar FPGAs, in packages as small as 6x6 mm, with support for PCIe and GigE.

High-speed Interfaces – Up to 70% faster differential I/O (vs. similar FPGAs) at 1.5 Gbps. 5 Gbps PCIe, 1 Gbps GigE and 1066 Mbps DDR3 memory interfaces also supported.

Built on Lattice Nexus platform – Up to 4x lower power vs. similar FPGAs. Up to 100x higher reliability, due to 100x lower Soft Error Rate (SER) from 28 nm FD-SOI technology. Extended density range and features available in the CertusPro-NX family.

Certus-NX

Features

  • Up to 65K logic cells, 3.3 Mb embedded memory, 128 18 x 18 multipliers, 380 programmable I/O, one lane of 5 Gbps PCIe, two lanes of 1 Gbps GigE, two ADCs (each 12-bit, 1 MSPS).
  • Packages as small as 6x6 mm, and in ball-pitch options of 0.5 and 0.8 mm.
  • Power modes – User selectable Low Power vs. High Performance modes, enabled by FD-SOI programmable back-bias.
  • Design security – ECDSA bitstream authentication, coupled with robust AES-256 encryption.
  • Instant-on configuration – I/O configures in 3 ms, and full-device as fast as 8 ms.
  • Available in Commercial, Industrial and Automotive (AEC-Q100 qualified) temperature grades.

Jump to

Family Table

Certus-NX and CertusPro-NX Device Selection Guide
Certus-NX Device Selection Guide CertusPro-NX Device Selection Guide
Features LFD2NX-9 LFD2NX-15 LFD2NX-17 LFD2NX-25 LFD2NX-28 LFD2NX-35 LFD2NX-40 LFD2NX-65 LFCPNX-50 LFCPNX-100
Logic Cells 9K 15K 17K 25K 28K 35K 39K 65K 52K 96K
Embedded Memory (EBR) Bits (kb) 270 864 432 1440 1044 1890 1512 2304 1728 3744
Large Memory (LRAM) Bits (kb) 1536 512 2560 512 1024 512 1024 1024 2048 3584
18 X 18 Multipliers 12 12 24 20 40 48 56 128 96 156
ADC Blocks 2 2 2 2 2 2 2 2 2 2
GPLL 2 2 2 2 3 2 3 2 3 4
PCIe Hard IP — — — — Gen2 Gen2 Gen2 Gen2 Gen3 Gen3
DDR Memory DDR3/DDR3L, LPDDR2 1066Mbps x 16 DDR3/3L, LPDDR2/LPDDR4 1066Mbps x64
Temperature Grades1 (ms) C, I, A C, I C, I, A C, I C, I, A C, I C, I, A C, I C, I, A C, I, A
0.5 mm Total I/O (Wide Range, High Performance, ADC2) / PCIe Lane
LFD2NX-9 LFD2NX-15 LFD2NX-17 LFD2NX-25 LFD2NX-28 LFD2NX-35 LFD2NX-40 LFD2NX-65 LFCPNX-50 LFCPNX-100
121 csfBGA (6 x 6 mm) 77(23,48,6)/0 — 77(23,48,6)/0 — 81(23,58,0)/1 — 81(23,58 0)/1 — —
256 ASG256 (9 x 9 mm) — — — — — — — — 165(75,84,6)/4 165(75,84,6)/4
0.8 mm Total I/O (Wide Range, High Performance, ADC2) / PCIe Lane

LFD2NX-9 LFD2NX-15 LFD2NX-17 LFD2NX-25 LFD2NX-28 LFD2NX-35 LFD2NX-40 LFD2NX-65 LFCPNX-50 LFCPNX-100
196 caBGA (12 x 12 mm) 77(23,48,6)/0 — 77(23,48,6)/0 — 156(92,58,6)/0 — 156(92,58,6)/0 — — —
256 caBGA (14 x 14 mm) — 205(159,40,6)/0 — 205(159,40,6)/0 191(111,74,6)/1 ​ 181(145,30,6)/1 191(111,74,6)/1 ​ 181(145,30,6)/1 — —
256 CBG256 (14 x 14 mm) — — — — — — — — 165(75,84,6)/4 165(75,84,6)/4
400 caBGA (17 x 17 mm) — 311(257,48,6)/0​ — 311(257,48,6)/0​ — 313(259,48,6)/0 — 313(259,48,6)/0 — —
484 BBG484 (19 x 19 mm) — — — — — 371(317,48,6)/1 — 371(317,48,6)/1 269(167,96,6)/4 305(167,132,6)/8
1.0 mm Total I/O (Wide Range, High Performance, ADC2) / PCIe Lane

LFD2NX-9 LFD2NX-15 LFD2NX-17 LFD2NX-25 LFD2NX-28 LFD2NX-35 LFD2NX-40 LFD2NX-65 LFCPNX-50 LFCPNX-100
484 BFG484 (23 x 23 mm)3 — — — — — — — — 269(167,96,6)/4 305(167,132,6)/4
672 LFG672 (27 x 27 mm)3 — — — — — — — — — 305(167,132,6)/8

1. C = Commercial, I = Industrial, A = Automotive
2. Each ADC pin count reflects using dedicated complement pair and vRef
3. Not available in Automotive Grade

Example Solutions

PCIe to SGMII Bridge Block Diagram with Certus-NXExpand Image

PCIe to GigE Bridge

  • Bridge processor to Ethernet via PCIe Gen2
  • Compact packages as small as 6x6 mm with PCIe and GigE support
  • Hard blocks for PCIe Gen2 eases development
PCIe Control Place Bridge Block Diagram with Certus-NXExpand Image

PCIe Control Plane Bridge

  • Bridge processor via PCIe Gen2 to multiple control plane peripherals (UART, SPI, I2C, MDIO, etc.) and board management functions
  • Packages with high # of programmable I/O per mm2 maximizes # of interfaces in a given form-factor
  • PCIe hard IP with built-in Multi-function support simplifies development
  • Instant-on configuration supports board management needs and PCIe boot-time requirements
Co:processing Block Diagram with Certus-NXExpand Image

Co-processing

  • Off-load CPU by using Certus-NX as a co-processor to accelerate complex functions
  • DDR3 & LPDDR2 interface support (up to 1066 Mbps) and on-chip embedded memory (up to 2.9 Mbit) provide multiple options for data buffering
  • Compact packages as small as 6x6 mm with PCIe and DDR memory interface support
Motor Control Block Diagram with Certus-NXExpand Image

Motor Control

  • Increase efficiency and performance of motor control functions
  • High reliability due to 100x lower Soft Error Rate (SER) from 28 nm FD-SOI technology
  • Industrial temperature support

Video

Certus-NX: Power Consumption Comparison
Expand Video

Certus-NX: Power Consumption Comparison

See a competitive power consumption demo comparing the power consumption of a Lattice Certus-NX running a 5 Gbps PCIe design with two similar competing FPGAs.

Design Resources

Development Kits & Boards

Our development boards & kits help streamline your design process

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Complete Design Flows, High Ease of Use

Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLENUMBERVERSIONDATEFORMATSIZE
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ADC User Guide for Nexus Platform
FPGA-TN-021292.21/6/2026PDF1.3 MB
Advanced Configuration Security Usage Guide for Nexus Platform
FPGA-TN-021761.56/23/2021PDF2.8 MB
Certus-NX 17K Pinout
FPGA-SC-020101.27/18/2024CSV7.5 KB
Certus-NX 28K Pinout
FPGA-SC-020601.07/18/2024CSV30.8 KB
Certus-NX 40K Pinout
FPGA-SC-020041.57/2/2025CSV12.1 KB
Certus-NX 9K Pinout
FPGA-SC-020591.07/18/2024CSV7.3 KB
Certus-NX 9K/17K/28K/40K Migration Table for 121csfBGA
FPGA-SC-020611.13/30/2025CSV18.6 KB
Certus-NX Family Data Sheet
FPGA-DS-020782.47/15/2025PDF2.9 MB
Certus-NX Hardware Checklist
FPGA-TN-021511.911/5/2025PDF1008.9 KB
Certus-Nx High Speed IO Interface
FPGA-TN-022161.77/15/2025PDF2.9 MB
Certus-NX Product Brochure
I02752.08/25/2021PDF547.7 KB
Common Programming and Configuration FAQs with Supplementary Concepts for CrossLink-NX, Certus-NX, and CertusPro-NX
FPGA-AN-020481.51/16/2025PDF1.8 MB
I2C Hardened IP Usage Guide for Nexus Platform
FPGA-TN-021421.35/31/2022PDF1.4 MB
I3C Controller Driver API Reference
FPGA-TN-023421.012/21/2023PDF894.8 KB
I3C Target Driver API Reference
FPGA-TN-023381.012/21/2023PDF769.7 KB
Lattice Memory Mapped Interface (LMMI) and Lattice Interrupt Interface (LINTR) User Guide
FPGA-UG-020391.25/31/2022PDF1.7 MB
Lattice OrCAD Capture Schematic Library
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.		FPGA-SC-020059.012/16/2025ZIP3.2 MB
Memory User Guide for Nexus Platform
FPGA-TN-020941.810/1/2025PDF2 MB
MIPI D-PHY Bandwidth Matrix and Implementation
FPGA-TN-020901.412/11/2025PDF957.3 KB
Multi-Boot User Guide for Nexus Platform
FPGA-TN-021452.48/27/2025PDF1.4 MB
Package Diagrams
FPGA-DS-020538.58/5/2025PDF9.4 MB
PCB Layout Recommendations for BGA Packages
FPGA-TN-020245.612/10/2024PDF6.2 MB
Power Management and Calculation for Certus-NX, CertusPro-NX, and MachXO5-NX Devices
FPGA-TN-022571.15/31/2022PDF1 MB
Single Event Upset (SEU) Report for Nexus Platform
FPGA-TN-021741.810/13/2025PDF453.7 KB
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-020762.310/13/2025PDF806.2 KB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-020415.212/11/2025PDF533.3 KB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-020282.612/10/2024PDF560.4 KB
sysCLOCK PLL Design and User Guide for Nexus Platform
FPGA-TN-020952.710/13/2025PDF1.9 MB
sysCONFIG User Guide for Nexus Platform
FPGA-TN-020993.57/15/2025PDF4.1 MB
sysDSP User Guide for Nexus Platform
FPGA-TN-020961.76/26/2024PDF1.3 MB
sysI/O User Guide for Nexus Platform
FPGA-TN-020672.810/13/2025PDF820.9 KB
Thermal Management
FPGA-TN-020445.812/11/2025PDF1.1 MB
TransFR Usage Guide for Nexus Platform
FPGA-TN-021731.16/24/2020PDF813.8 KB
Triple-Speed Ethernet Driver API Reference
FPGA-TN-023411.26/26/2025PDF568.1 KB
Using TraceID
FPGA-TN-020842.912/11/2025PDF491.6 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

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Certus-NX Family Data Sheet
FPGA-DS-020782.47/15/2025PDF2.9 MB
TITLENUMBERVERSIONDATEFORMATSIZE
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ADC User Guide for Nexus Platform
FPGA-TN-021292.21/6/2026PDF1.3 MB
Adding Scalable Power and Thermal Management to Nexus FPGAs
FPGA-AN-020791.01/31/2024PDF1.3 MB
Advanced Configuration Security Usage Guide for Nexus Platform
Access this document via a Technical Support Request after signing in to the Lattice website. Complete the request form via this link, please click here.		FPGA-TN-021762.19/23/2025WEB
Advanced Configuration Security Usage Guide for Nexus Platform
FPGA-TN-021761.56/23/2021PDF2.8 MB
Certus-NX Hardware Checklist
FPGA-TN-021511.911/5/2025PDF1008.9 KB
Certus-Nx High Speed IO Interface
FPGA-TN-022161.77/15/2025PDF2.9 MB
Certus-NX-17K/40K Migration to 196caBGA Package
FPGA-TN-023761.07/18/2024PDF300.6 KB
Common Programming and Configuration FAQs with Supplementary Concepts for CrossLink-NX, Certus-NX, and CertusPro-NX
FPGA-AN-020481.51/16/2025PDF1.8 MB
I2C Hardened IP Usage Guide for Nexus Platform
FPGA-TN-021421.35/31/2022PDF1.4 MB
I3C Controller Driver API Reference
FPGA-TN-023421.012/21/2023PDF894.8 KB
I3C Target Driver API Reference
FPGA-TN-023381.012/21/2023PDF769.7 KB
Memory User Guide for Nexus Platform
FPGA-TN-020941.810/1/2025PDF2 MB
Migrating Designs from AMD CPLD/FPGA Devices to Lattice FPGA Devices
FPGA-AN-020811.18/27/2024PDF2.6 MB
MIPI D-PHY Bandwidth Matrix and Implementation
FPGA-TN-020901.412/11/2025PDF957.3 KB
Multi-Boot User Guide for Nexus Platform
FPGA-TN-021452.48/27/2025PDF1.4 MB
PCB Layout Recommendations for BGA Packages
FPGA-TN-020245.612/10/2024PDF6.2 MB
Power Management and Calculation for Certus-NX, CertusPro-NX, and MachXO5-NX Devices
FPGA-TN-022571.15/31/2022PDF1 MB
Single Event Upset (SEU) Report for Nexus Platform
FPGA-TN-021741.810/13/2025PDF453.7 KB
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-020762.310/13/2025PDF806.2 KB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-020415.212/11/2025PDF533.3 KB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-020282.612/10/2024PDF560.4 KB
sysCLOCK PLL Design and User Guide for Nexus Platform
FPGA-TN-020952.710/13/2025PDF1.9 MB
sysCONFIG User Guide for Nexus Platform
FPGA-TN-020993.57/15/2025PDF4.1 MB
sysDSP User Guide for Nexus Platform
FPGA-TN-020961.76/26/2024PDF1.3 MB
sysI/O User Guide for Nexus Platform
FPGA-TN-020672.810/13/2025PDF820.9 KB
Thermal Management
FPGA-TN-020445.812/11/2025PDF1.1 MB
TransFR Usage Guide for Nexus Platform
FPGA-TN-021731.16/24/2020PDF813.8 KB
Triple-Speed Ethernet Driver API Reference
FPGA-TN-023411.26/26/2025PDF568.1 KB
Using TraceID
FPGA-TN-020842.912/11/2025PDF491.6 KB
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
Certus-NX 15K Pinout
FPGA-SC-020700.817/15/2025CSV16.1 KB
Certus-NX 17K Pinout
FPGA-SC-020101.27/18/2024CSV7.5 KB
Certus-NX 25K Pinout
FPGA-SC-020710.817/15/2025CSV16.2 KB
Certus-NX 28K Pinout
FPGA-SC-020601.07/18/2024CSV30.8 KB
Certus-NX 35K Pinout
FPGA-SC-020800.747/15/2025CSV22 KB
Certus-NX 40K Pinout
FPGA-SC-020041.57/2/2025CSV12.1 KB
Certus-NX 65K Pinout
FPGA-SC-020810.747/15/2025CSV22 KB
Certus-NX 9K Pinout
FPGA-SC-020591.07/18/2024CSV7.3 KB
Certus-NX 9K/17K/28K/40K Migration Table for 121csfBGA
FPGA-SC-020611.13/30/2025CSV18.6 KB
CrossLink-NX and Certus-NX Pin Migration
FPGA-TN-022181.03/22/2024PDF495.5 KB
FPGA-SC-02103-1-0-Certus-NX-Migration-Table-caBGA196
FPGA-SC-021031.07/15/2025CSV29.1 KB
Package Diagrams
FPGA-DS-020538.58/5/2025PDF9.4 MB
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Lattice Memory Mapped Interface (LMMI) and Lattice Interrupt Interface (LINTR) User Guide
FPGA-UG-020391.25/31/2022PDF1.7 MB
PCIe Basic Demo on Certus-NX Versa Evaluation Board - User Guide
FPGA-UG-021331.111/30/2021PDF1.5 MB
sysCLOCK PLL Design and User Guide for Nexus Platform
FPGA-TN-020952.710/13/2025PDF1.9 MB
sysCONFIG User Guide for Nexus Platform
FPGA-TN-020993.57/15/2025PDF4.1 MB
TITLENUMBERVERSIONDATEFORMATSIZE
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Design Advisory for Nexus LVDS-based SGMII
FPGA-DA2506011.06/3/2025PDF77.4 KB
Notification of Changes to CrossLink-NX™ Data Sheet and Certus-NX™ Data Sheet
PCN02A-221.04/4/2022PDF329.6 KB
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Lattice OrCAD Capture Schematic Library
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.		FPGA-SC-020059.012/16/2025ZIP3.2 MB
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Certus-NX Product Brochure
I02752.08/25/2021PDF547.7 KB
Lattice FPGA Product Selector Guide
v25.3.01/6/2026PDF717 KB
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Certus-NX Innovates General-Purpose FPGAs
1.06/24/2020PDF255.3 KB
Random Bin Picking Based On Structured-Light 3D Scanning
WP00432.05/22/2025PDF3.7 MB
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[BSDL] LFD2NX-15
FPGA-MD-021120.807/29/2025ZIP18.4 KB
[BSDL] LFD2NX-17
FPGA-MD-020811.25/6/2025ZIP10.3 KB
[BSDL] LFD2NX-25
FPGA-MD-021130.87/15/2025ZIP18.4 KB
[BSDL] LFD2NX-28
FPGA-MD-020641.1510/1/2024ZIP12.7 KB
[BSDL] LFD2NX-35
FPGA-MD-021160.808/27/2025ZIP13 KB
[BSDL] LFD2NX-40
FPGA-MD-020081.165/10/2023BSM44 KB
[BSDL] LFD2NX-65
FPGA-MD-021170.808/28/2025ZIP12.9 KB
[BSDL] LFD2NX-9
FPGA-MD-02065 1.1510/1/2024ZIP12.3 KB
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Certus-NX Device Family Delphi Models
FPGA-MD-020231.27/15/2025ZIP812.4 KB
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[IBIS AMI] LFD2NX
Access this document via a Technical Support Request after signing in to the Lattice website. Complete the request form via this link, please click here.		FPGA-MD-021151.08/13/2025WEB
[IBIS] LFD2NX-15/25
FPGA-MD-021100.87/15/2025ZIP14.9 MB
[IBIS] LFD2NX-35/65
FPGA_MD_021090.87/15/2025ZIP14.9 MB
[IBIS] LFD2NX-9/17/28/40
FPGA-MD-020091.412/16/2025ZIP12.4 MB

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