Platform Manager

Centralize control functions with scalable power management

Revolutionary power management architecture – Easily manage up to 36 rails using distributed power sense and centralized controls. Slash time to market and debug time through fault logging.

Change your algorithm, not your board – Instead of reworking your PCB, simply reprogram your Platform Manager device to quickly handle design changes.

Don’t throttle the silicon – Platform Manager’s precision voltage scaling and VID features enable easy control of complex, power-hungry ASICs and SoCs.

Features

  • Centralized power-up/down sequencing control and power supply sensing
  • Lower chip power dissipation using voltage scaling / VID
  • Precision voltage control (<10 mV accuracy) with closed-loop trimming
  • Capture voltage faults (primary cause) within 100 µs with 0.2% (typ) accuracy and store in on-chip flash
  • Quickly modify monitoring thresholds, sequence or timing… even when the system is in the field

Jump to

Family Table

Platform Manager Device Selector Guide

Parameters LPTM10-1247 LPTM10-12107
Analog Inputs - Single-Ended 5 0
Analog Inputs - Differential 7 12
Total Analog Inputs 12 12
Dedicated Open Drain Outputs 12 12
Dedicated Digital Inputs 4 4
Digital I/O 31 91
Total Digital I/O 47 107
Margin and Trim 6 8
MOSFET Driver Outputs 4 4
CPLD MacroCells 48 48
FPGA - LUT-s 640 640
Package 128-pin TQFP 208-ball ftBGA

Design Resources

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Development Kits & Boards

Our development boards & kits help streamline your design process

Application Notes

Learn how to get the most from our line-up of FPGAs / development boards

Programming Hardware

Take the strain out of in-system programming & in-circuit reconfiguration with our programming hardware

Complete Design Flows, High Ease of Use

Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLENUMBERVERSIONDATEFORMATSIZE
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Controlling and Monitoring Power-One Bricks and SIPs with Lattice Power Manager Devices
AN605601.14/17/2008PDF216.1 KB
Creating Platform Manager Designs with PAC-Designer and Lattice Diamond Software
TN125901.03/4/2013PDF4.9 MB
Extending the VMON Input Range of Power/Platform Management Devices
FPGA-AN-020312.59/21/2021PDF1.1 MB
Fail-Safe Sequencing During Field Upgrades Source Files
DT60881.26/6/2012ZIP591.5 KB
Fail-Safe Sequencing During Field Upgrades with Platform Manager
AN608801.26/6/2012PDF1.1 MB
High-side Current Sensing Techniques for Power Manager Devices
AN604901.14/17/2008PDF70.9 KB
Implementing Power Supply Sequencers with Power/Platform Management Devices and PAC-Designer LogiBuilder
AN604201.210/7/2011PDF277 KB
Interfacing the Trim Output of Power Manager II Devices to DC-DC Converters
AN60741.24/7/2015PDF3.1 MB
ispPAC-POWR1220AT8 I2C Hardware Verification Utility
AN606701.011/21/2005PDF563.7 KB
Lattice OrCAD Capture Schematic Library
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
FPGA-SC-020059.012/16/2025ZIP3.2 MB
Monitoring and Controlling Negative Power Supplies with Power Manager Devices
AN605102.14/17/2008PDF67.9 KB
Optimizing the Accuracy of ispPAC Power Manager Timers
AN607601.012/12/2007PDF215.9 KB
Platform Manager Data Sheet
FPGA-DS-020771.42/14/2020PDF7.5 MB
Powering Up and Programming the ispPAC-POWR1014/A
AN607501.14/11/2011PDF190.4 KB
Powering Up and Programming the ispPAC-POWR1220AT8
AN607301.14/21/2011PDF171.2 KB
Powering Up and Programming the ispPAC-POWR607
AN607801.14/21/2011PDF1.3 MB
Powering Up and Programming the ProcessorPM ispPAC-POWR605
AN608201.14/21/2011PDF1.1 MB
Programmable Comparator Options for ispPAC-POWR1220AT8
AN606901.011/21/2005PDF259.4 KB
Programming the ispPAC-POWR1220AT8 in a JTAG Chain Using the ATDI Pin
AN606801.12/28/2011PDF245.8 KB
Scalable Centralized Power Management Source Files
DT60891.26/6/2012ZIP520.7 KB
Scalable Centralized Power Management with Field Upgrade Support
AN608901.26/6/2012PDF1.1 MB
Stable Operation of DC-DC Converters with Power Manager Closed Loop Trim
AN60771.110/8/2014PDF676.8 KB
Using PAC-Designer's Power Manager Waveform Editor
AN605401.011/23/2005PDF276.3 KB
Using Power MOSFETs with Power/Platform Management Devices
AN60481.38/29/2017PDF734.6 KB
Using the HVOUT Simulator Utility to Estimate FET Ramp Times
AN607001.011/21/2005PDF540.1 KB
Using the Platform Manager Successfully
TN122301.18/17/2012PDF949.4 KB
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
Platform Manager Data Sheet
FPGA-DS-020771.42/14/2020PDF7.5 MB
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
Controlling and Monitoring Power-One Bricks and SIPs with Lattice Power Manager Devices
AN605601.14/17/2008PDF216.1 KB
Creating Platform Manager Designs with PAC-Designer and Lattice Diamond Software
TN125901.03/4/2013PDF4.9 MB
Extending the VMON Input Range of Power/Platform Management Devices
FPGA-AN-020312.59/21/2021PDF1.1 MB
Fail-Safe Sequencing During Field Upgrades Source Files
DT60881.26/6/2012ZIP591.5 KB
Fail-Safe Sequencing During Field Upgrades with Platform Manager
AN608801.26/6/2012PDF1.1 MB
High-side Current Sensing Techniques for Power Manager Devices
AN604901.14/17/2008PDF70.9 KB
Implementing Power Supply Sequencers with Power/Platform Management Devices and PAC-Designer LogiBuilder
AN604201.210/7/2011PDF277 KB
Interfacing the Trim Output of Power Manager II Devices to DC-DC Converters
AN60741.24/7/2015PDF3.1 MB
ispPAC-POWR1220AT8 I2C Hardware Verification Utility
AN606701.011/21/2005PDF563.7 KB
Monitoring and Controlling Negative Power Supplies with Power Manager Devices
AN605102.14/17/2008PDF67.9 KB
Optimizing the Accuracy of ispPAC Power Manager Timers
AN607601.012/12/2007PDF215.9 KB
Powering Up and Programming the ispPAC-POWR1014/A
AN607501.14/11/2011PDF190.4 KB
Powering Up and Programming the ispPAC-POWR1220AT8
AN607301.14/21/2011PDF171.2 KB
Powering Up and Programming the ispPAC-POWR607
AN607801.14/21/2011PDF1.3 MB
Powering Up and Programming the ProcessorPM ispPAC-POWR605
AN608201.14/21/2011PDF1.1 MB
Programmable Comparator Options for ispPAC-POWR1220AT8
AN606901.011/21/2005PDF259.4 KB
Programming the ispPAC-POWR1220AT8 in a JTAG Chain Using the ATDI Pin
AN606801.12/28/2011PDF245.8 KB
Scalable Centralized Power Management Source Files
DT60891.26/6/2012ZIP520.7 KB
Scalable Centralized Power Management with Field Upgrade Support
AN608901.26/6/2012PDF1.1 MB
Stable Operation of DC-DC Converters with Power Manager Closed Loop Trim
AN60771.110/8/2014PDF676.8 KB
Using PAC-Designer's Power Manager Waveform Editor
AN605401.011/23/2005PDF276.3 KB
Using Power MOSFETs with Power/Platform Management Devices
AN60481.38/29/2017PDF734.6 KB
Using the HVOUT Simulator Utility to Estimate FET Ramp Times
AN607001.011/21/2005PDF540.1 KB
Using the Platform Manager Successfully
TN122301.18/17/2012PDF949.4 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

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BSCAN1 - Multiple Boundary Scan Port Addressable Buffer - Documentation
FPGA-RD-021057.41/29/2021PDF993.7 KB
BSCAN1 - Multiple Boundary Scan Port Addressable Buffer - Source Code
RD10017.34/18/2011ZIP152.4 KB
BSCAN2 - Multiple Boundary Scan Port Linker - Source Code
RD10024.63/13/2014ZIP2.6 MB
BSCAN2 - Multiple Scan Port Linker - Documentation
FPGA-RD-021064.91/29/2021PDF918.1 KB
Closed Loop Power Supply Trimming Documentation
RD10781.012/6/2010PDF278.2 KB
Closed Loop Power Supply Trimming Source Code
RD10781.012/6/2010ZIP269.4 KB
Error Logging Using Platform Manager Documentation
RD10771.09/28/2010PDF422.5 KB
Error Logging Using Platform Manager Source Files
RD10771.09/28/2010ZIP372.9 KB
GPIO Expander, Documentation
RD10651.34/12/2011PDF280.6 KB
GPIO Expander, Source Code
RD10651.34/12/2011ZIP195.5 KB
I2C (Inter-Integrated Circuit) Master Controller - Documentation
RD10055.83/6/2014PDF987.4 KB
I2C (Inter-Integrated Circuit) Master Controller - Source Code
RD10055.91/10/2015ZIP809.7 KB
I2C (Inter-Integrated Circuit) Slave/Peripheral - Documentation
RD10541.612/1/2014PDF801.5 KB
I2C (Inter-Integrated Circuit) Slave/Peripheral - Source Code
RD10541.612/12/2014ZIP764.8 KB
I2C Slave to SPI Master Bridge - Documentation
FPGA-RD-021111.21/29/2021PDF863.9 KB
I2C Slave to SPI Master Bridge - Source Code
RD10941.112/23/2011ZIP180.4 KB
Long Delay Timers Using Platform Manager Documentation
RD10791.19/28/2010PDF874.1 KB
Long Delay Timers Using Platform Manager Source Files
RD10791.09/28/2010ZIP683.9 KB
OrCAD Capture (.dsn) format schematics
19/28/2010ZIP0.7 KB
Platform Manager Dev Kit Initial Demo Source Files
RD1.11/26/2011ZIP1.1 MB
Platform Manager Dev Kit Power Supply Voltage Control (VID) Demo Source Files
1.012/6/2010ZIP1.1 MB
Power Management Bus Reference Design - Source Code
RD11001.112/23/2011ZIP378.3 KB
Power Management Bus Reference Design Documentation
FPGA-RD-020971.21/22/2021PDF1.1 MB
PWM Fan Controller
RD10601.69/10/2014PDF481.5 KB
PWM Fan Controller - Source Code
RD10601.71/16/2015ZIP2.9 MB
Serial Peripheral Interface (SPI) - Documentation
RD10751.112/23/2011PDF158.7 KB
Serial Peripheral Interface (SPI) - Source Code
RD10751.112/23/2011ZIP124.8 KB
SPI GPIO Expander - Documentation
RD10731.112/23/2010PDF212.5 KB
SPI GPIO Expander - Source Code
RD10731.112/23/2010ZIP161.6 KB
Temperature Monitor Using Platform Manager Documentation
RD10801.09/28/2010PDF330 KB
Temperature Monitor Using Platform Manager Source Files
RD10801.09/28/2010ZIP256.7 KB
UART (Universal Asynchronous Receiver/Transmitter) - Source Code
7/15/2025ZIP772.5 KB
UART (Universal Asynchronous Receiver/Transmitter) - User Guide
FPGA-RD-022701.87/15/2025PDF741.9 KB
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MachXO 300 mm Fab Transition Circuit Observations Mitigation
PB13772.06/12/2017PDF82.7 KB
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ACN03D-11 Withdrawal of ACN03C-11
Material Set
ANC03D-1114/1/2011PDF796.6 KB
PCN 03A-15 Alternate Qualified Foundry / Mask Set and Alternate Qualified Material Sets for Platform Manager Products
Foundry, Mask Set, Material Set
PCN03A-152.011/23/2015PDF318.2 KB
PCN 03A-15 LPTM10 New MASK SET Yield and Parametric Analysis
PCN03A-151.011/23/2015PDF779.6 KB
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Lattice OrCAD Capture Schematic Library
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
FPGA-SC-020059.012/16/2025ZIP3.2 MB
TITLENUMBERVERSIONDATEFORMATSIZE
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Lattice FPGA Product Selector Guide
v25.3.01/6/2026PDF717 KB
Platform Manager Product Brochure
I02081.04/10/2012PDF2.8 MB
Platform Manager Product Brochure (Chinese)
I0208C1.06/4/2012PDF2.9 MB
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FTG208_LPTM10
Rev G16/9/2022PDF141.7 KB
Lattice Platform Manager Product Family Qualification Summary
C11/21/2015PDF579.3 KB
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Fast and Efficient Board and Power Management Solutions (Chinese Language)
1.04/1/2011PDF502.3 KB
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LPTM10_12107_XO640
1.0110/8/2014BSM30.3 KB
LPTM10_1247_MO640
1.0110/8/2014BSM24.9 KB
Platform Manager 128 TQFP BSDL Files
1.12/26/2013ZIP8.4 KB
Platform Manager 208 ftBGA BSDL Files
1.12/27/2014ZIP10 KB
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Selecting Power and Platform Manager Devices Excel Spreadsheet Tool
1.13/19/2012ZIP63.1 KB

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