ispMACH 4000V/ZProductDetailPagecd1fa365-43d2-47c2-b000-718c990a59c2aafbc2a7-f44e-4d0a-bdc6-4c111e40ad4bWebpage/Products/FPGAandCPLD/ispMACH4000VZ/Products/FPGAandCPLD/ispMACH4000VZThe ispMACH 4000V/Z family integrates up to 512 macrocells that support individual clock reset, preset and clock enable controls that operate at SuperFAST™ frequencies of up to 400 MHz.The ispMACH 4000V/Z family integrates up to 512 macrocells that support individual clock reset, preset and clock enable controls that operate at SuperFAST™ frequencies of up to 400 MHz.The ispMACH 4000 family blends the ispLSI® 2000 and ispMACH 4A architectures to offer a SuperFAST™ CPLD solution with low power.SuperFAST™ performance at low powerHigh density, high performance - The ispMACH 4000V/Z family integrates up to 512 macrocells that support individual clock reset, preset and clock enable controls that operate at SuperFAST frequencies of up to 400 MHz. Better together - The ispMACH 4000 family blends the ispLSI 2000 and ispMACH 4A architectures to offer a SuperFAST CPLD solution with low power. If only shopping for clothes was so easy - With its Global Routing Pool and Output Routing Pool, the ispMACH 4000 family delivers excellent First-Time-Fit, timing predictability, routing, pin-out retention and density migration.ispMACH 4000V/Z, lattice ispMACH 4000V/Z, ispMACH 4000V/Z CPLD, lattice semi ispMACH 4000V/Z CPLD
High density, high performance – The ispMACH 4000V/Z family integrates up to 512 macrocells that support individual clock reset, preset and clock enable controls that operate at SuperFAST™ frequencies of up to 400 MHz.
Better together – The ispMACH 4000 family blends the ispLSI® 2000 and ispMACH 4A architectures to offer a SuperFAST™ CPLD solution with low power.
If only shopping for clothes was so easy – With its Global Routing Pool and Output Routing Pool, the ispMACH 4000 family delivers excellent First-Time-Fit, timing predictability, routing, pin-out retention and density migration.
Features
1.8 V core for low dynamic power
5 V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces
JTAG In-System Programmable (ISP™)
Available in TQFP, ftBGA, fpBGA and csBGA packages
Automotive temperature range support -40 to +130 °C Junction (Tj)
Lattice OrCAD Capture Schematic Library This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
Lattice OrCAD Capture Schematic Library This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
