Search

LatticeXP2

Get flexible, get flexiFLASH

Related Products

The logical choice – LatticeXP2 devices combine up to 40 K LUTs with non-volatile Flash cells to enable instant-on performance across a feature-set optimized for high-volume, low cost applications

Never fear, FlashBAK™ is here – Backup data from the embedded block RAMs to Flash memory on command and prevent data loss on system power-down.

Configure, reconfigure, repeat – The LatticeXP2 family supports live update technology with TransFR™ and secure 128-bit AES Encryption as well as dual-boot technologies.

Features

  • Up to 885 Kbits sysMEM™ embedded block RAM and up to 83 Kbits distributed RAM
  • sysCLOCK™ PLLs up to four analog PLLs per device that enable clock multiply, divide and phase shifting
  • Three to eight sysDSP blocks for high performance multiply and accumulate.
  • Pre-engineered source synchronous IOs for DDR/DDR2 up to 200 MHz and 7:1 LVDS interface support up to 600 Mbps
  • Available in csBGA, TQFP, PQFP and BGA packaging

Jump to

Family Table

LatticeXP2 Device Selection Guide

PARAMETERS XP2-5 XP2-8 XP2-17 XP2-30 XP2-40
LUTs (K) 5 8 17 29 40
EBR SRAM Blocks 9 12 15 21 48
EBR SRAM (Kbits) 166 221 276 387 885
Distributed RAM (Kbits) 10 18 35 56 83
sysDSP Blocks 3 4 5 7 8
18x18 Multipliers 12 16 20 28 32
PLL + DLL 2 + 2 2 + 2 4 + 2 4 + 2 4 + 2
DDR Support (Mbps) DDR/2 400 DDR/2 400 DDR/2 400 DDR/2 400 DDR/2 400
Configuration Memory Internal Flash Internal Flash Internal Flash Internal Flash Internal Flash
Dual Boot1 Yes Yes Yes Yes Yes
Bit-stream Encryption Yes Yes Yes Yes Yes
Core Vcc 1.2 V Yes Yes Yes Yes Yes
Temp C Yes Yes Yes Yes Yes
Temp I Yes Yes Yes Yes Yes
Temp AEC-Q100 Yes Yes Yes    
0.5 mm Spacing I/O Count
  XP2-5 XP2-8 XP2-17 XP2-30 XP2-40
132-pin csBGA (8 x 8 mm) 86 86      
144-pin TQFP (20 x 20 mm) 100 100      
208-Pin PQFP (28 x 28 mm) 146 146 146    
1.0 mm Spacing I/O Count
  XP2-5 XP2-8 XP2-17 XP2-30 XP2-40
256-ball ftBGA (17 x 17 mm) 172 201 201 201  
484-ball fpBGA (23 x 23 mm)     358 363 363
672-ball fpBGA (27 x 27 mm)       472 540

1. Dual Boot Supported with external boot Flash.

Lattice Automotive (AEC-Q100 qualified) LatticeXP2 Device Selection Guide

Parameters LA-XP2-5 LA-XP2-8 LA-XP2-17
LUTs (K) 5 8 17
Distributed RAM (Kbits) 10 18 35
EBR SRAM (Kbits) 166 221 276
EBR SRAM Blocks (9 Kbits) 9 12 15
sysDSP Blocks 3 4 5
18 x 18 Multipliers 12 16 20
VCC Voltage 1.2 1.2 1.2
GPLL 2 2 4
Maximum Available I/O 172 201 201
0.5 mm Spacing I/O Count

LA-XP2-5 LA-XP2-8 LA-XP2-17
132-pin csBGA (8 x 8 mm) 86 86  
144-pin TQFP (20 x 20 mm) 100 100  
1.0 mm Spacing I/O Count

LA-XP2-5 LA-XP2-8 LA-XP2-17
208-ball PQFP (28 x 28 mm) 146 146 146
256-ball ftBGA (17 x 17 mm) 172 201 201

Design Resources

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Development Kits & Boards

Our development boards & kits help streamline your design process

Complete Design Flows, High Ease of Use

Programming Hardware

Take the strain out of in-system programming & in-circuit reconfiguration with our programming hardware

Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
High-Speed PCB Design Considerations
FPGA-TN-021786.48/21/2024PDF3.5 MB
LA-LatticeXP2 Automotive Family Data Sheet
DS10241.52/28/2015PDF6.5 MB
Lattice OrCAD Capture Schematic Library
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.		FPGA-SC-020059.012/16/2025ZIP3.2 MB
LatticeXP2 132 csBGA Migration
1.02/29/2008CSV5.8 KB
LatticeXP2 144 TQFP Migration
1.02/29/2008CSV6.3 KB
LatticeXP2 208 PQFP Migration
1.02/29/2008CSV12.8 KB
LatticeXP2 256 ftBGA Migration
1.02/29/2008CSV19.5 KB
LatticeXP2 484 fpBGA Migration
1.02/29/2008CSV28.6 KB
LatticeXP2 672 fpBGA Migration
1.08/19/2008CSV28.9 KB
LatticeXP2 Advanced Security Programming Usage Guide
TN12121.011/29/2010PDF1.1 MB
LatticeXP2 Configuration Encryption and Security Usage Guide
TN11421.25/1/2008PDF893.2 KB
LatticeXP2 Dual Boot Feature
TN12201.18/27/2012PDF1.5 MB
LatticeXP2 Family Data Sheet
FPGA-DS-020882.58/21/2021PDF4.2 MB
LatticeXP2 Family Data Sheet (Japanese Language Version)
DS1009J1.89/6/2012PDF5.1 MB
LatticeXP2 Hardware Checklist Technical Note
TN11431.39/18/2013PDF356.9 KB
LatticeXP2 High-Speed I/O Interface
TN11381.53/27/2017PDF5 MB
LatticeXP2 Memory Usage Guide
FPGA-UG-020802.33/29/2021PDF2.9 MB
LatticeXP2 Slave SPI Port Usage Guide
TN12131.26/5/2012PDF2.7 MB
LatticeXP2 Soft Error Detection (SED) Usage Guide
FPGA-TN-022532.25/14/2021PDF706.4 KB
LatticeXP2 sysCLOCK PLL Design and Usage Guide
FPGA-TN-020921.49/30/2012PDF1.1 MB
LatticeXP2 sysCONFIG Usage Guide
TN11412.01/9/2014PDF1.3 MB
LatticeXP2 sysDSP Usage Guide
TN11401.02/1/2007PDF1.2 MB
LatticeXP2 sysIO Usage Guide
TN11361.36/28/2010PDF811.1 KB
LatticeXP2-17 Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.		1.1a8/10/2011CSV20.1 KB
LatticeXP2-30 Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.		1.18/10/2011CSV26.9 KB
LatticeXP2-40 Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.		1.1a8/10/2011CSV25.3 KB
LatticeXP2-5 Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.		1.1a8/10/2011CSV12.1 KB
LatticeXP2-8 Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.		1.1a8/10/2011CSV13.3 KB
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-021984.612/11/2025PDF1.6 MB
Package Diagrams
FPGA-DS-020538.58/5/2025PDF9.4 MB
PCB Layout Recommendations for BGA Packages
FPGA-TN-020245.612/10/2024PDF6.2 MB
Power Decoupling and Bypass Filtering for Programmable Devices
FPGA-TN-021151.11/26/2022PDF708.9 KB
Power Estimation and Management for LatticeXP2 Devices Technical Note
TN11391.02/1/2007PDF1.2 MB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-020415.212/11/2025PDF533.3 KB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-020282.612/10/2024PDF560.4 KB
Thermal Management
FPGA-TN-020445.812/11/2025PDF1.1 MB
Wafer-Level Chip-Scale Package Guide
FPGA-TN-023121.16/23/2022PDF236.5 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

TITLENUMBERVERSIONDATEFORMATSIZE
Select All
Die Sale Datasheet
DS10511.03/2/2015PDF731.3 KB
LA-LatticeXP2 Automotive Family Data Sheet
DS10241.52/28/2015PDF6.5 MB
LatticeXP2 Family Data Sheet
FPGA-DS-020882.58/21/2021PDF4.2 MB
LatticeXP2 Family Data Sheet (Japanese Language Version)
DS1009J1.89/6/2012PDF5.1 MB
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
High-Speed PCB Design Considerations
FPGA-TN-021786.48/21/2024PDF3.5 MB
High-Speed PCB Design Considerations (Chinese Language Version)
TN1033C06.15/23/2011PDF434.6 KB
LatticeXP2 Advanced Security Programming Usage Guide
TN12121.011/29/2010PDF1.1 MB
LatticeXP2 Configuration Encryption and Security Usage Guide
TN11421.25/1/2008PDF893.2 KB
LatticeXP2 Dual Boot Feature
TN1220J1.05/22/2013PDF802.6 KB
LatticeXP2 Dual Boot Feature
TN12201.18/27/2012PDF1.5 MB
LatticeXP2 Hardware Checklist Technical Note
TN11431.39/18/2013PDF356.9 KB
LatticeXP2 High-Speed I/O Interface
TN11381.53/27/2017PDF5 MB
LatticeXP2 High-Speed I/O Interface (Japanese Language Version)
TN113801.11/18/2009PDF1.4 MB
LatticeXP2 Memory Usage Guide
FPGA-UG-020802.33/29/2021PDF2.9 MB
LatticeXP2 Memory Usage Guide (Japanese Language Version)
TN113701.72/15/2009PDF1.9 MB
LatticeXP2 Slave SPI Port Usage Guide
TN12131.26/5/2012PDF2.7 MB
LatticeXP2 Soft Error Detection (SED) Usage Guide
FPGA-TN-022532.25/14/2021PDF706.4 KB
LatticeXP2 sysCLOCK PLL Design and Usage Guide
FPGA-TN-020921.49/30/2012PDF1.1 MB
LatticeXP2 sysCLOCK PLL Design and Usage Guide (Japanese Language Version)
TN112601.01/23/2009PDF844.3 KB
LatticeXP2 sysCONFIG Usage Guide
TN11412.01/9/2014PDF1.3 MB
LatticeXP2 sysCONFIG Usage Guide (Japanese Language Version)
TN114101.41/20/2009PDF291.6 KB
LatticeXP2 sysDSP Usage Guide
TN11401.02/1/2007PDF1.2 MB
LatticeXP2 sysDSP Usage Guide (Japanese Language Version)
TN114001.01/17/2009PDF1.2 MB
LatticeXP2 sysIO Usage Guide
TN11361.36/28/2010PDF811.1 KB
LatticeXP2 sysIO Usage Guide (Japanese Language Version)
TN113601.11/18/2009PDF307.1 KB
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-021984.612/11/2025PDF1.6 MB
PCB Layout Recommendations for BGA Packages
FPGA-TN-020245.612/10/2024PDF6.2 MB
Power Decoupling and Bypass Filtering for Programmable Devices
FPGA-TN-021151.11/26/2022PDF708.9 KB
Power Estimation and Management for LatticeXP2 Devices Technical Note
TN11391.02/1/2007PDF1.2 MB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-020415.212/11/2025PDF533.3 KB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-020282.612/10/2024PDF560.4 KB
Thermal Management
FPGA-TN-020445.812/11/2025PDF1.1 MB
Wafer-Level Chip-Scale Package Guide
FPGA-TN-023121.16/23/2022PDF236.5 KB
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
LatticeXP2 132 csBGA Migration
1.02/29/2008CSV5.8 KB
LatticeXP2 144 TQFP Migration
1.02/29/2008CSV6.3 KB
LatticeXP2 208 PQFP Migration
1.02/29/2008CSV12.8 KB
LatticeXP2 256 ftBGA Migration
1.02/29/2008CSV19.5 KB
LatticeXP2 484 fpBGA Migration
1.02/29/2008CSV28.6 KB
LatticeXP2 672 fpBGA Migration
1.08/19/2008CSV28.9 KB
LatticeXP2-17 Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.		1.1a8/10/2011CSV20.1 KB
LatticeXP2-30 Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.		1.18/10/2011CSV26.9 KB
LatticeXP2-40 Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.		1.1a8/10/2011CSV25.3 KB
LatticeXP2-5 Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.		1.1a8/10/2011CSV12.1 KB
LatticeXP2-8 Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.		1.1a8/10/2011CSV13.3 KB
Package Diagrams
FPGA-DS-020538.58/5/2025PDF9.4 MB
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
LatticeXP2 Advanced Evaluation Board User's Guide
Describes the features and function of the LatticeXP2 Advanced Evaluation Board. Includes Schematics.		EB3001.53/11/2011PDF2.2 MB
LatticeXP2 Brevia 2 Development Kit User's Guide
EB671.011/18/2011PDF1.6 MB
LatticeXP2 Standard Evaluation Board User Manual
Describes the features and functionality of the LatticeXP2 Standard Evaluation Board		EB2901.52/11/2010PDF1.7 MB
PCI IP Core User's Guide
PCI Core User Guide for LatticeSC, LatticeECP3, LatticeECP2/M, LatticeECP/EC, LatticeXP, Mach XO, and MachXO2		IPUG189.211/8/2010PDF4.6 MB
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
8b/10b Encoder/Decoder - Documentation
FPGA-RD-021031.51/29/2021PDF940.3 KB
8b/10b Encoder/Decoder - Source Code
1.41/29/2021ZIP1.9 MB
Arbitration and Switching Between Bus Masters - Documentation
FPGA-RD-021041.21/21/2021PDF952.5 KB
Arbitration and Switching Between Bus Masters - Source code
RD10671.12/22/2010ZIP284 KB
BSCAN1 - Multiple Boundary Scan Port Addressable Buffer - Documentation
FPGA-RD-021057.41/29/2021PDF993.7 KB
BSCAN1 - Multiple Boundary Scan Port Addressable Buffer - Source Code
RD10017.34/18/2011ZIP152.4 KB
BSCAN2 - Multiple Boundary Scan Port Linker - Source Code
RD10024.63/13/2014ZIP2.6 MB
BSCAN2 - Multiple Scan Port Linker - Documentation
FPGA-RD-021064.91/29/2021PDF918.1 KB
CompactFlash Controller - Documentation
FPGA-RD-020881.41/22/2021PDF1.7 MB
CompactFlash Controller - Source Code
RD10401.411/8/2010ZIP1.5 MB
Control Link Serial Interface - Documentation
FPGA-RD-020891.51/22/2021PDF810.2 KB
Control Link Serial Interface - Source Code
RD10511.411/8/2010ZIP240.7 KB
Fast Page Mode SDRAM Controller - Documentation
FPGA-RD-020902.41/22/2021PDF887.1 KB
Fast Page Mode SDRAM Controller - Source Code
RD10142.311/8/2010ZIP110.4 KB
GPIO Expander, Documentation
RD10651.34/12/2011PDF280.6 KB
GPIO Expander, Source Code
RD10651.34/12/2011ZIP195.5 KB
HDLC Controller for FPGAs - Documentation
RD103801.19/4/2008PDF1.1 MB
HDLC Controller for FPGAs - Source Code
RD10381.09/4/2008ZIP1.2 MB
I2C (Inter-Integrated Circuit) Master Controller - Documentation
RD10055.83/6/2014PDF987.4 KB
I2C (Inter-Integrated Circuit) Master Controller - Source Code
RD10055.91/10/2015ZIP809.7 KB
I2C (Inter-Integrated Circuit) Slave/Peripheral - Documentation
RD10541.612/1/2014PDF801.5 KB
I2C (Inter-Integrated Circuit) Slave/Peripheral - Source Code
RD10541.612/12/2014ZIP764.8 KB
I2C Controller for Serial EEPROMs - Documentation
RD10062.63/5/2014PDF767.9 KB
I2C Controller for Serial EEPROMs - Source Code
RD10062.71/12/2015ZIP613.5 KB
I2C Master with WISHBONE Bus Interface - Documentation
RD10461.61/15/2015PDF1.4 MB
I2C Master with WISHBONE Bus Interface - Source Code
RD10461.82/1/2016ZIP1.4 MB
NAND Flash Controller Design - Documentation
FPGA-RD-020951.31/22/2021PDF1.6 MB
Parallel to MIPI CSI-2 TX Bridge - Documentation
FPGA-RD-021321.68/19/2021PDF1.1 MB
Parallel to MIPI CSI-2 TX Bridge - Source Code
RD11831.51/1/2015ZIP1.2 MB
Parallel to MIPI DSI TX Bridge - Documentation
FPGA-RD-021331.61/31/2021PDF1.2 MB
Parallel to MIPI DSI TX Bridge - Source Code
RD11841.51/1/2015ZIP2.6 MB
PCI Target 32-bit/33MHz
FPGA-RD-021343.61/31/2021PDF1.8 MB
PCI to NOR Flash Interface
RD10501.13/10/2010PDF367.9 KB
PCI/WISHBONE Bridge
FPGA-RD-021351.42/5/2021PDF1.2 MB
Power Supply Fault Logging - Documentation
RD10621.26/30/2010PDF127.8 KB
Power Supply Fault Logging - Source Code
RD10621.26/30/2010ZIP123.4 KB
PWM Fan Controller
RD10601.69/10/2014PDF481.5 KB
RGMII to GMII Bridge - Source Code
7/15/2025ZIP382.7 KB
RGMII to GMII Bridge Reference Design - User Guide
FPGA-RD-021362.67/15/2025PDF257.7 KB
SD Flash Controller - Documentation
RD10481.11/29/2010PDF1.7 MB
Simple Sigma-Delta ADC - Source Code
1.59/26/2018ZIP1.5 MB
Simple Sigma-Delta ADC, Documentation
FPGA-RD-020471.61/30/2020PDF971 KB
WISHBONE UART - Documentation
FPGA-RD-021371.72/5/2021PDF1.1 MB
WISHBONE UART - Source Code
RD10421.612/1/2014ZIP58.5 MB
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
ACN03D-11 Withdrawal of ACN03C-11
Material Set		ANC03D-1114/1/2011PDF796.6 KB
Courtesy Notification of Additional Ejector Pin Sites on Select BGA Packages
5/22/2013PDF252.9 KB
PCN 03C13 Alternate Qualified Assembly Test Site Alternate Qualified Material Sets ASE Taiwan
Assembly Site, Material Set		PCN03C1.011/14/2014PDF212.8 KB
PCN 09A-12 Affected Devices
Assembly Site		PCN09A-121.05/14/2012XLSX121 KB
PCN 09A-12 Alternate Qualified Material Set, Assembly Site for Select Lattice Families
PCN09A-121.05/14/2012PDF160.2 KB
PCN 09A-12 Customer Characterization Report
PCN09A-121.05/14/2012PDF551.7 KB
PCN 09A-12 Frequently Asked Questions
PCN09A-121.05/11/2012PDF178.9 KB
PCN 09A-12 Material Set Changes
Assembly Site		PCN09A-121.05/14/2012XLSX121 KB
PCN02B-12 Notification of a Revision to the LatticeXP2, LA-LatticeXP2 and LatticeECP2/M Data Sheets
Data Sheet		PCN02B-121.02/6/2012PDF181.6 KB
PCN03A-13 Alternate Qualified Assembly and Material Sets for Select Devices
PCN03A-136/28/2013PDF202.5 KB
PCN03A-13 Device Characterization Report
PCN03A-136/28/2013PDF981.3 KB
PCN03A-13 FAQs
PCN03A-136/28/2013PDF458.3 KB
PCN03A-14 Characterization Report
PCN03A-141.04/4/2014PDF919.5 KB
PCN03A-14 FAQ
PCN03A-141.04/4/2014PDF452.5 KB
PCN03A-14 Material Set Table
PCN03A-141.04/4/2014XLSX26.9 KB
PCN03B-14 Notification of Intent to Utilize an Alternate Qualified Assembly Site/Test Site and/or Alternate Qualified Material Sets for Select Lattice Products
PCN03B-141.011/21/2014PDF229.9 KB
PCN03C-13 Affected Part Number and Material Sets
PCN03C-136/28/2013XLSX51.2 KB
PCN03C-14 Affected Part Number List
PCN03C-141.04/4/2014XLSX50.8 KB
PCN05A-17 Affected Parts List
1.010/18/2017XLSX14.9 KB
PCN05A-17 Halogen-Free substrate at ASEM
1.210/27/2017PDF268 KB
PCN06A-14 Characterization Report
PCN06A-141.010/3/2014PDF563.7 KB
PCN06A-14 Material Set Table
PCN06A-141.010/3/2014XLSX13.7 KB
PCN06B-14 Notification of Intent to Utilize an Alternate Qualified Assembly Site/Test Site and Alternate Qualified Material Sets for Select Lattice Products
PCN06B-141.011/21/2014PDF229.5 KB
PCN06C-11 Withdrawal of PCN06B-11
Material Set		PCN06C-111.08/1/2011PDF838.5 KB
PCN06C-14 Affected Device List
PCN06C-141.010/3/2014XLSX29.6 KB
PCN07C-11 Withdrawal of PCN07B-11
Material Set		PCN07C-111.08/1/2011PDF917.9 KB
PCN08A13_AffectedDevices
Other		PCN08A-1319/26/2013XLSX78.2 KB
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
Lattice OrCAD Capture Schematic Library
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.		FPGA-SC-020059.012/16/2025ZIP3.2 MB
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
Automotive Solutions Product Brief
I01648.06/5/2009PDF2.4 MB
Lattice FPGA Product Selector Guide
v25.3.01/6/2026PDF717 KB
LatticeXP2 FPGA Family Product Brief
I01923.04/24/2012PDF2.4 MB
LatticeXP2 FPGA Family Product Brief (Chinese)
I0192C2.06/1/2010PDF1.8 MB
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
FN484
Rev K16/8/2022PDF30.4 KB
FN672
Rev L16/8/2022PDF154.1 KB
FTN256_LAXP2_LAMXO
Rev H16/9/2022PDF141.3 KB
FTN256_v1_Cu_XO_XP2
Rev. R16/9/2022PDF150.2 KB
LatticeXP2 Product Family Qualification Summary
E11/1/2012PDF226.7 KB
MN132_Cu_all
Rev R16/21/2022PDF149.6 KB
QN_YN208
Rev E112/21/2021PDF21.9 KB
TN_TG_TQ144 Cu_wire all
Rev E112/21/2021PDF107.1 KB
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
Embedded Display Control Using FPGAs
1.03/1/2010PDF249.6 KB
Embedded Display Control Using FPGAs (Traditional Chinese Language)
5/22/2013PDF1.6 MB
FPGA Design Security Issues: Using Lattice FPGAs to Achieve High Design Security
9/1/2007PDF259.2 KB
Interfacing Analog to Digital Converters to FPGAs
1.011/7/2007PDF202.3 KB
Third Generation Non-Volatile FPGAs Enable System on Chip Functionality
6/1/2007PDF329.1 KB
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
[BSDL] LFXP2 30E_FPBGA484
1.0112/1/2009BSM78.9 KB
[BSDL] LFXP2 30E_FPBGA672
1.0112/1/2009BSM90.6 KB
[BSDL] LFXP2 30E_FTBGA256
1.0112/1/2009BSM62.9 KB
[BSDL] LFXP2 40E_FPBGA484
1.0112/1/2009BSM84.7 KB
[BSDL] LFXP2 40E_FPBGA672
1.0112/1/2009BSM100.5 KB
[BSDL] LFXP2 5E_CSBGA132
1.0112/1/2009BSM32.4 KB
[BSDL] LFXP2 5E_FTBGA256
1.0112/1/2009BSM40.7 KB
[BSDL] LFXP2 5E_PQFP208
1.0112/1/2009BSM38.3 KB
[BSDL] LFXP2 5E_TQFP144
1.0112/1/2009BSM33.5 KB
[BSDL] LFXP2 8E TQFP144
1.0112/1/2009BSM38.1 KB
[BSDL] LFXP2 8E_CSBGA132
1.0112/1/2009BSM36.9 KB
[BSDL] LFXP2 8E_FPBGA484
1.0112/1/2009BSM55.5 KB
[BSDL] LFXP2 8E_FTBGA256
1.0112/1/2009BSM46.9 KB
[BSDL] LFXP2 8E_PQFP208
1.0112/1/2009BSM42.9 KB
[BSDL] LFXP217E 208 PQFP
1.0112/1/2009BSM50.5 KB
[BSDL] LFXP217E 256 FPBGA
1.0112/1/2009BSM54.5 KB
[BSDL] LFXP217E 484 FPBGA
1.0112/1/2009BSM70.1 KB
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
XP2 Device Family DELPHI Models
1.04/9/2009ZIP297.9 KB
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
[IBIS] LatticeXP2 IBIS Model
2.41/27/2009IBS34.1 MB
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
TransFR Demo for LatticeXP2 Standard Evaluation Board
Demonstrates the TransFR feature of the LatticeXP2 FPGA. Update your FPGA with no down-time!		8/10/2007ZIP394.5 KB

Support

Technical Support

Need Help? We're Here to Assist You

Find The Software & IP Licenses You Need

Quality & Reliability

Reference Material to Help Answer Your Questions

Outside Services to Help Get The Job Done

Lattice Semiconductor

ABOUT LATTICE

SALES

SUPPORT

FOLLOW