MachXO

Versatile and non-volatile PLD for bridging, infinitely reconfigurable I/O expansion.

Give Complexity the Boot – Designed to remove the complexity of choosing between CPLDs and low-capacity FPGAs – with glue logic, bus bridging, bus interfacing, power-up control, and control logic, you no longer need to choose.

Expand Your Interfaces – With up to 271 IOs, MachXO are perfect for a wide range of applications that require general purpose I/O expansion, interface bridging and power-up management functions.

To Infinite Reconfigurability and Beyond – Single chip solution featuring background programmable internal Flash memory and the ability for in-field logic updates during system configuration using TransFR™.

Features

  • Up to 27.6 Kbits sysMEM™ embedded block RAM and up to 7.7Kbits distributed RAM
  • SRAM based logic can be reconfigured in milliseconds using JTAG port
  • IOs support LVCMOS, LVTTL, PCI, LVDS, Bus-LVDS, LVPECL, RSDS
  • Up to two analog PLLs per device that enable clock multiplication, division, and phase shifting
  • Available in TQFP, csBGA, caBGA and ftBGA packages

Jump to

Family Table

MachXO Device Selection Guide

Parameters LCMXO256E LCMXO256C LCMXO640E LCMXO640C LCMXO1200E LCMXO1200C LCMXO2280E LCMXO2280C
Density LUTs 256 256 640 640 1200 1200 2280 2280
EBR SRAM Blocks - - - - 1 1 3 3
EBR SRAM (Kbits) - - - - 9.2 9.2 27.6 27.6
Distributed RAM (Kbits) 2 2 6.1 6.1 6.4 6.4 7.7 7.7
PLL + DLL - - - - 1 + 0 1 + 0 2 + 0 2 + 0
Configuration Memory Internal Flash Internal Flash Internal Flash Internal Flash Internal Flash Internal Flash Internal Flash Internal Flash
Dual Boot1 Yes Yes Yes Yes Yes Yes Yes Yes
Core Vcc 1.2 V Yes - Yes - Yes - Yes -
Core Vcc 1.8 - 3.3 V - Yes - Yes - Yes - Yes
Temp C Yes Yes Yes Yes Yes Yes Yes Yes
Temp I Yes Yes Yes Yes Yes Yes Yes Yes
Temp AEC-Q100 Yes Yes Yes Yes Yes - Yes -
0.5 mm Spacing I/O Count
  LCMXO256E LCMXO256C LCMXO640E LCMXO640C LCMXO1200E LCMXO1200C LCMXO2280E LCMXO2280C
100-ball csBGA (8 x 8 mm) 78 78 74 74
132-ball csBGA (8 x 8 mm) 101 101 101 101 101 101
100-pin TQFP (14 x 14 mm) 78 78 74 74 73 73 73 73
144-pin TQFP (20 x 20 mm) 113 113 113 113 113 113
0.8 mm Spacing I/O Count
  LCMXO256E LCMXO256C LCMXO640E LCMXO640C LCMXO1200E LCMXO1200C LCMXO2280E LCMXO2280C
256-ball caBGA (14 x 14 mm) 159 159 211 211 211 211
1.0 mm Spacing I/O Count
  LCMXO256E LCMXO256C LCMXO640E LCMXO640C LCMXO1200E LCMXO1200C LCMXO2280E LCMXO2280C
256-ball ftBGA (17 x 17 mm) 159 159 211 211 211 211
324-ball ftBGA (19 x 19 mm) 271 271

1. Dual Boot supported with external boot Flash.

Lattice Automotive (AEC-Q100 qualified) MachXO Device Selection Guide

Parameters LAMXO256E/C LAMXO640E/C LAMXO1200E LAMXO2280E
LUTs 256 647 1200 2280
Dist. RAM (Kbits) 2.0 6.0 6.25 7.5
EBR SRAM (Kbits) 0 0 9.2 27.6
Number of EBR SRAM Blocks (9 Kbits) 0 0 1 3
VCC Voltage 1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V 1.2 1.2
NUmber of PLLs 0 0 1 2
Max. I/O 78 159 211 271
0.5 mm Spacing I/O Count
LAMXO256E/C LAMXO640E/C LAMXO1200E LAMXO2280E
100-pin Lead-Free TQFP (14 x 14 mm) 78 74 73 73
144-pin Lead-Free TQFP (20 x 20 mm) - 113 113 113
1.0 mm Spacing I/O Count
LAMXO256E/C LAMXO640E/C LAMXO1200E LAMXO2280E
256-ball Lead-Free ftBGA (17 x 17 mm) - 159 211 211
324-ball Lead-Free ftBGA (19 x 19 mm) - - - 271

Design Resources

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Development Kits & Boards

Our development boards & kits help streamline your design process

Complete Design Flows, High Ease of Use

Programming Hardware

Take the strain out of in-system programming & in-circuit reconfiguration with our programming hardware

Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLENUMBERVERSIONDATEFORMATSIZE
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Input Hysteresis in Lattice CPLD and FPGA Devices
TN11121.19/1/2006PDF465.6 KB
LA-MachXO Automotive Family Data Sheet
FPGA-DS-020701.61/22/2021PDF3 MB
Lattice OrCAD Capture Schematic Library
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
FPGA-SC-020059.012/16/2025ZIP3.2 MB
Linking or Selecting Ports with BSCAN2
FPGA-AN-020131.11/10/2022PDF680.9 KB
MachXO Density Migration
TN10971.09/1/2005PDF41.2 KB
MachXO Family Data Sheet
FPGA-DS-020713.37/30/2022PDF3.3 MB
MachXO Family Data Sheet (Japanese Language Version)
DS100202.86/1/2009PDF1.8 MB
MachXO JTAG Programming and Configuration User Guide
FPGA-TN-021671.511/8/2022PDF906.6 KB
MachXO sysCLOCK Design and Usage Guide
TN10891.59/26/2011PDF1 MB
MachXO sysIO Usage Guide
TN10911.59/15/2010PDF425.4 KB
Memory Usage Guide for MachXO Devices
TN10921.510/1/2010PDF1.4 MB
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-021984.612/11/2025PDF1.6 MB
Package Diagrams
FPGA-DS-020538.58/5/2025PDF9.4 MB
Parallel Flash Programming and FPGA Configuration
Also download the implementation files for AN8077.
AN80771.33/1/2015PDF2.4 MB
Parallel Flash Programming and FPGA Configuration - Source Code
For use with Application Note - AN8077
AN80771.31/4/2013RAR1.4 MB
PCB Layout Recommendations for BGA Packages
FPGA-TN-020245.612/10/2024PDF6.2 MB
Power Decoupling and Bypass Filtering for Programmable Devices
FPGA-TN-021151.11/26/2022PDF708.9 KB
Power Estimation and Management for MachXO Devices
TN10901.19/1/2007PDF1.9 MB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-020415.212/11/2025PDF533.3 KB
Thermal Management
FPGA-TN-020445.812/11/2025PDF1.1 MB
USB Programming and Circuit Guide
FPGA-AN-020151.21/22/2021PDF1.4 MB
Using a Discrete Crystal as a PLD Clock Source
FPGA-AN-020161.16/21/2021PDF672.5 KB
Using Multiple Boundary Scan Port Linker (BSCAN2)
FPGA-AN-020171.11/9/2022PDF774.3 KB
Wafer-Level Chip-Scale Package Guide
FPGA-TN-023121.16/23/2022PDF236.5 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

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Die Sale Datasheet
DS10511.03/2/2015PDF731.3 KB
LA-MachXO Automotive Family Data Sheet
FPGA-DS-020701.61/22/2021PDF3 MB
MachXO Family Data Sheet
FPGA-DS-020713.37/30/2022PDF3.3 MB
MachXO Family Data Sheet (Japanese Language Version)
DS100202.86/1/2009PDF1.8 MB
TITLENUMBERVERSIONDATEFORMATSIZE
Select All
Input Hysteresis in Lattice CPLD and FPGA Devices
TN11121.19/1/2006PDF465.6 KB
Linking or Selecting Ports with BSCAN2
FPGA-AN-020131.11/10/2022PDF680.9 KB
MachXO Density Migration
TN10971.09/1/2005PDF41.2 KB
MachXO JTAG Programming and Configuration User Guide
FPGA-TN-021671.511/8/2022PDF906.6 KB
MachXO sysCLOCK Design and Usage Guide
TN10891.59/26/2011PDF1 MB
MachXO sysIO Usage Guide
TN10911.59/15/2010PDF425.4 KB
Memory Usage Guide for MachXO Devices
TN10921.510/1/2010PDF1.4 MB
Migrating Designs from AMD CPLD/FPGA Devices to Lattice FPGA Devices
FPGA-AN-020811.18/27/2024PDF2.6 MB
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-021984.612/11/2025PDF1.6 MB
Parallel Flash Programming and FPGA Configuration
Also download the implementation files for AN8077.
AN80771.33/1/2015PDF2.4 MB
Parallel Flash Programming and FPGA Configuration - Source Code
For use with Application Note - AN8077
AN80771.31/4/2013RAR1.4 MB
PCB Layout Recommendations for BGA Packages
FPGA-TN-020245.612/10/2024PDF6.2 MB
Power Decoupling and Bypass Filtering for Programmable Devices
FPGA-TN-021151.11/26/2022PDF708.9 KB
Power Estimation and Management for MachXO Devices
TN10901.19/1/2007PDF1.9 MB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-020415.212/11/2025PDF533.3 KB
Thermal Management
FPGA-TN-020445.812/11/2025PDF1.1 MB
USB Programming and Circuit Guide
FPGA-AN-020151.21/22/2021PDF1.4 MB
Using a Discrete Crystal as a PLD Clock Source
FPGA-AN-020161.16/21/2021PDF672.5 KB
Using Multiple Boundary Scan Port Linker (BSCAN2)
FPGA-AN-020171.11/9/2022PDF774.3 KB
Wafer-Level Chip-Scale Package Guide
FPGA-TN-023121.16/23/2022PDF236.5 KB
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Package Diagrams
FPGA-DS-020538.58/5/2025PDF9.4 MB
TITLENUMBERVERSIONDATEFORMATSIZE
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MachXO 2280 Breakout Board Evaluation Kit User's Guide
FPGA-EB-020381.26/28/2021PDF2.4 MB
PCI IP Core User's Guide
PCI Core User Guide for LatticeSC, LatticeECP3, LatticeECP2/M, LatticeECP/EC, LatticeXP, Mach XO, and MachXO2
IPUG189.211/8/2010PDF4.6 MB
POWR1014A Breakout Board Evaluation Kit User's Guide
EB6401.12/13/2012PDF1.3 MB
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8b/10b Encoder/Decoder - Documentation
FPGA-RD-021031.51/29/2021PDF940.3 KB
8b/10b Encoder/Decoder - Source Code
1.41/29/2021ZIP1.9 MB
Advanced SDR SDRAM Controller - Design Documentation
FPGA-RD-020874.91/22/2021PDF1.1 MB
Advanced SDR SDRAM Controller - Source Code
RD10104.89/12/2014ZIP495.7 KB
Arbitration and Switching Between Bus Masters - Documentation
FPGA-RD-021041.21/21/2021PDF952.5 KB
Arbitration and Switching Between Bus Masters - Source code
RD10671.12/22/2010ZIP284 KB
BSCAN1 - Multiple Boundary Scan Port Addressable Buffer - Documentation
FPGA-RD-021057.41/29/2021PDF993.7 KB
BSCAN1 - Multiple Boundary Scan Port Addressable Buffer - Source Code
RD10017.34/18/2011ZIP152.4 KB
BSCAN2 - Multiple Boundary Scan Port Linker - Source Code
RD10024.63/13/2014ZIP2.6 MB
BSCAN2 - Multiple Scan Port Linker - Documentation
FPGA-RD-021064.91/29/2021PDF918.1 KB
CompactFlash Controller - Documentation
FPGA-RD-020881.41/22/2021PDF1.7 MB
CompactFlash Controller - Source Code
RD10401.411/8/2010ZIP1.5 MB
Control Link Serial Interface - Documentation
FPGA-RD-020891.51/22/2021PDF810.2 KB
Control Link Serial Interface - Source Code
RD10511.411/8/2010ZIP240.7 KB
Delta Sigma ADC - Documentation
RD10631.010/19/2009PDF110.9 KB
Fast Page Mode SDRAM Controller - Documentation
FPGA-RD-020902.41/22/2021PDF887.1 KB
Fast Page Mode SDRAM Controller - Source Code
RD10142.311/8/2010ZIP110.4 KB
GPIO Expander, Documentation
RD10651.34/12/2011PDF280.6 KB
GPIO Expander, Source Code
RD10651.34/12/2011ZIP195.5 KB
HDLC Controller for FPGAs - Documentation
RD103801.19/4/2008PDF1.1 MB
HDLC Controller for FPGAs - Source Code
RD10381.09/4/2008ZIP1.2 MB
I2C (Inter-Integrated Circuit) Master Controller - Documentation
RD10055.83/6/2014PDF987.4 KB
I2C (Inter-Integrated Circuit) Master Controller - Source Code
RD10055.91/10/2015ZIP809.7 KB
I2C (Inter-Integrated Circuit) Slave/Peripheral - Documentation
RD10541.612/1/2014PDF801.5 KB
I2C (Inter-Integrated Circuit) Slave/Peripheral - Source Code
RD10541.612/12/2014ZIP764.8 KB
I2C Controller for Serial EEPROMs - Documentation
RD10062.63/5/2014PDF767.9 KB
I2C Controller for Serial EEPROMs - Source Code
RD10062.71/12/2015ZIP613.5 KB
I2C Master with WISHBONE Bus Interface - Documentation
RD10461.61/15/2015PDF1.4 MB
I2C Master with WISHBONE Bus Interface - Source Code
RD10461.82/1/2016ZIP1.4 MB
I2C Slave to SPI Master Bridge - Documentation
FPGA-RD-021111.21/29/2021PDF863.9 KB
I2C Slave to SPI Master Bridge - Source Code
RD10941.112/23/2011ZIP180.4 KB
I2S Controller with WISHBONE Interface Reference Design - Source Code
RD11011.13/1/2014ZIP1.6 MB
I2S Controller with WISHBONE Interface Reference Design Documentation
RD11011.13/1/2014PDF2.4 MB
IDE/ATA Interface Controller - WISHBONE Compatible - Documentation
RD10951.06/28/2010PDF769.8 KB
IDE/ATA Interface Controller - WISHBONE Compatible - Source Code
RD10951.06/28/2010ZIP756.3 KB
LatticeMico8 to WISHBONE Interface Adapter - Documentation
RD10431.12/23/2010PDF126.2 KB
LatticeMico8 to WISHBONE Interface Adapter - Source Code
RD10431.12/23/2010ZIP109.3 KB
LatticeMico8 v3.0 Verilog
3.02/19/2008ZIP1.1 MB
LatticeMico8 v3.1 Verilog
RD10263.14/9/2010ZIP913.9 KB
LED/OLED Driver - Documentation
RD11031.13/1/2014PDF989.6 KB
LED/OLED Driver - Source code
RD11031.13/1/2014ZIP1.4 MB
LPC (Low Pin Count) Bus Controller - Source Code
RD10491.64/12/2011ZIP517.2 KB
LPC (Low Pin Count) Bus Controller Reference Design - Documentation
FPGA-RD-021141.71/21/2021PDF1 MB
MachXO 2280 Breakout Board Evaluation Kit Source Code
This demo includes the Lattice Diamond project source for the preprogrammed demonstration design. It programs the LCMXO2280-FTN256 with a counter circuit using the embedded oscillator timer and sysIO Buffers configured for LED drive
1.03/21/2011ZIP10.7 KB
MDIO (Management Data Input/Output Interface) Peripheral - WISHBONE Compatible
FPGA-RD-021301.21/31/2021PDF1021 KB
MDIO Peripheral - WISHBONE Compatible - Source Code
RD10741.12/19/2010ZIP354.1 KB
NAND Flash Controller - Source Code
RD10551.411/8/2014ZIP912.7 KB
NAND Flash Controller Design - Documentation
FPGA-RD-020951.31/22/2021PDF1.6 MB
NOR Flash Memory Controller with WISHBONE Interface - Documentation
FPGA-RD-020961.21/22/2021PDF1.6 MB
NOR Flash Memory Controller with WISHBONE Interface - Source Code
RD10871.111/8/2010ZIP198.1 KB
PCI Target (33MHz, 32 Bit ) - Source Code
RD10083.58/20/2013ZIP980.4 KB
PCI Target 32-bit/33MHz
FPGA-RD-021343.61/31/2021PDF1.8 MB
PCI to NOR Flash Interface
RD10501.13/10/2010PDF367.9 KB
PCI to NOR Flash Interface - Source Code
RD10501.13/10/2010ZIP3.8 MB
PCI/WISHBONE Bridge
FPGA-RD-021351.42/5/2021PDF1.2 MB
PCI/WISHBONE Bridge - Source Code
RD10451.34/10/2011ZIP4.5 MB
Power Management Bus Reference Design - Source Code
RD11001.112/23/2011ZIP378.3 KB
Power Management Bus Reference Design Documentation
FPGA-RD-020971.21/22/2021PDF1.1 MB
Power Supply Fault Logging - Documentation
RD10621.26/30/2010PDF127.8 KB
Power Supply Fault Logging - Source Code
RD10621.26/30/2010ZIP123.4 KB
PWM Fan Controller
RD10601.69/10/2014PDF481.5 KB
PWM Fan Controller - Source Code
RD10601.71/16/2015ZIP2.9 MB
RD1026 LatticeMico8 Microcontroller User's Guide
2.111/8/2014PDF2.1 MB
Read and Write Usercode - Documentation
RD10411.49/17/2014PDF831.5 KB
Read and Write Usercode - Source Code
RD10411.33/1/2014ZIP618.2 KB
SD Flash Controller - Documentation
RD10481.11/29/2010PDF1.7 MB
SD Flash Controller Using SD Bus - Documentation
RD10881.43/12/2014PDF1.4 MB
SD Flash Controller Using SD Bus - Source Code
RD10881.43/12/2014ZIP5 MB
Serial Peripheral Interface (SPI) - Documentation
RD10751.112/23/2011PDF158.7 KB
Serial Peripheral Interface (SPI) - Source Code
RD10751.112/23/2011ZIP124.8 KB
Simple Sigma-Delta ADC - Source Code
1.59/26/2018ZIP1.5 MB
Simple Sigma-Delta ADC, Documentation
FPGA-RD-020471.61/30/2020PDF971 KB
Single-Wire Controller for Digital Temp Sensors Reference Design - Source Code
RD10991.011/8/2010ZIP513.1 KB
Single-Wire Controller for Digital Temp. Sensors Reference Design - Documentation
FPGA-RD-020991.11/22/2021PDF1.1 MB
SMBus Controller Reference Design - Documentation
FPGA-RD-021001.11/22/2021PDF1.3 MB
SMBus Controller Reference Design Source Code
RD10981.011/8/2010ZIP2.2 MB
SPI Flash Controller with Wear Leveling
FPGA-RD-021011.11/29/2021PDF1 MB
SPI Flash Controller with Wear Leveling - Source code
RD11021.011/8/2010ZIP952.2 KB
SPI GPIO Expander - Documentation
RD10731.112/23/2010PDF212.5 KB
SPI GPIO Expander - Source Code
RD10731.112/23/2010ZIP161.6 KB
SPI WISHBONE Controller - Documentation
RD10441.73/1/2014PDF960 KB
SPI WISHBONE Controller - Source Code
RD10441.81/12/2015ZIP477.7 KB
UART (Universal Asynchronous Receiver/Transmitter) - Source Code
7/15/2025ZIP772.5 KB
Wake on LAN - Documentation
RD10961.06/24/2010PDF311.6 KB
Wake on LAN - Source Code
RD10961.06/24/2010ZIP283.1 KB
WISHBONE UART - Documentation
FPGA-RD-021371.72/5/2021PDF1.1 MB
WISHBONE UART - Source Code
RD10421.612/1/2014ZIP58.5 MB
WISHBONE-Compatible LCD Controller - Documentation
FPGA-RD-021021.31/29/2021PDF918.3 KB
WISHBONE-Compatible LCD Controller - Source Code
RD10531.211/8/2010ZIP140.9 KB
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MachXO 300 mm Fab Transition Circuit Observations Mitigation
PB13772.06/12/2017PDF82.7 KB
TITLENUMBERVERSIONDATEFORMATSIZE
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ACN 05A-13 XO Transfer
Mask Set
ACN05A-137/11/2013PDF118.7 KB
ACN03D-11 Withdrawal of ACN03C-11
Material Set
ANC03D-1114/1/2011PDF796.6 KB
PCN 02A-15 Affected_OPN_Listing
Discontinuance
3.08/12/2015XLSX310.4 KB
PCN 02A-15 SnPb and Select Mature Family Discontinuance
1.06/18/2015PDF316.9 KB
PCN 03C13 Alternate Qualified Assembly Test Site Alternate Qualified Material Sets ASE Taiwan
Assembly Site, Material Set
PCN03C1.011/14/2014PDF212.8 KB
PCN 09A-12 Affected Devices
Assembly Site
PCN09A-121.05/14/2012XLSX121 KB
PCN 09A-12 Alternate Qualified Material Set, Assembly Site for Select Lattice Families
PCN09A-121.05/14/2012PDF160.2 KB
PCN 09A-12 Frequently Asked Questions
PCN09A-121.05/11/2012PDF178.9 KB
PCN 09A-12 Material Set Changes
Assembly Site
PCN09A-121.05/14/2012XLSX121 KB
PCN02A-15 Frequently Asked Questions
2.06/18/2015DOCX60.8 KB
PCN03A-13 Alternate Qualified Assembly and Material Sets for Select Devices
PCN03A-136/28/2013PDF202.5 KB
PCN03A-13 Device Characterization Report
PCN03A-136/28/2013PDF981.3 KB
PCN03A-13 FAQs
PCN03A-136/28/2013PDF458.3 KB
PCN03A-14 Characterization Report
PCN03A-141.04/4/2014PDF919.5 KB
PCN03A-14 FAQ
PCN03A-141.04/4/2014PDF452.5 KB
PCN03A-14 Material Set Table
PCN03A-141.04/4/2014XLSX26.9 KB
PCN03B-14 Notification of Intent to Utilize an Alternate Qualified Assembly Site/Test Site and/or Alternate Qualified Material Sets for Select Lattice Products
PCN03B-141.011/21/2014PDF229.9 KB
PCN03C-13 Affected Part Number and Material Sets
PCN03C-136/28/2013XLSX51.2 KB
PCN03C-14 Affected Part Number List
PCN03C-141.04/4/2014XLSX50.8 KB
PCN05A-14 Affected Part Number List
PCN05A-141.06/6/2014XLSX18.6 KB
PCN05A-14 Characterization Report
PCN05A-141.06/6/2014PDF499.2 KB
PCN05A-14 FAQ
PCN05A-141.06/6/2014PDF193.9 KB
PCN05A-14 Notification of Intent to Utilize an Alternate Qualified Foundry and Alternate Qualified Mask Sets for the MachXO Products
Foundry, Mask Set
PCN05A-141.12/5/2016PDF152.8 KB
PCN05A-17 Affected Parts List
1.010/18/2017XLSX14.9 KB
PCN05A-17 Halogen-Free substrate at ASEM
1.210/27/2017PDF268 KB
PCN06A-14 Characterization Report
PCN06A-141.010/3/2014PDF563.7 KB
PCN06A-14 Material Set Table
PCN06A-141.010/3/2014XLSX13.7 KB
PCN06B-14 Notification of Intent to Utilize an Alternate Qualified Assembly Site/Test Site and Alternate Qualified Material Sets for Select Lattice Products
PCN06B-141.011/21/2014PDF229.5 KB
PCN06C-11 Withdrawal of PCN06B-11
Material Set
PCN06C-111.08/1/2011PDF838.5 KB
PCN06C-14 Affected Device List
PCN06C-141.010/3/2014XLSX29.6 KB
PCN07A-14 Automotive XO foundry transfer
PCN07A-141.012/18/2014PDF430.8 KB
PCN07A-14 FAQ
Foundry, Mask Set
PCN07A-141.012/18/2014PDF89.6 KB
PCN07A-14 LA-MachXO Product Family AEC-Q100 Qualification Summary
PCN07A-141.012/18/2014PDF638.8 KB
PCN07C-11 Withdrawal of PCN07B-11
Material Set
PCN07C-111.08/1/2011PDF917.9 KB
PCN08A13_AffectedDevices
Other
PCN08A-1319/26/2013XLSX78.2 KB
PCN14A-09 MachXO2280 324-ftBGA ASEM AQAS AQMS - Japanese Language
PCN14A-0918/1/2009PDF132.1 KB
PCN14A-09 Notification of Intent to Utilize AQAS and AQMS for MachXO 324-ftBGA Devices
PCN14A-0918/1/2009PDF41.8 KB
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Lattice OrCAD Capture Schematic Library
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
FPGA-SC-020059.012/16/2025ZIP3.2 MB
TITLENUMBERVERSIONDATEFORMATSIZE
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Lattice FPGA Product Selector Guide
v25.3.01/6/2026PDF717 KB
MachXO Control Development Kit Brochure
I02061.010/19/2009PDF1007.2 KB
MachXO Mini Development Kit Product Brief
I01991.02/23/2009PDF815.3 KB
MachXO Product Brief
I01767.01/14/2013PDF1.3 MB
MachXO Product Brief (Chinese)
I0176C8.01/14/2013PDF1.3 MB
MachXO Product Brief (Japanese)
I0176J7.04/2/2010PDF1.2 MB
Ultra Low Density FPGAs Brochure
I0229B8/14/2013PDF2.1 MB
TITLENUMBERVERSIONDATEFORMATSIZE
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BN256_XO
Rev R16/9/2022PDF151.4 KB
FTN256_LAXP2_LAMXO
Rev H16/9/2022PDF141.3 KB
FTN256_v1_Cu_XO_XP2
Rev. R16/9/2022PDF150.2 KB
FTN324
Rev P16/9/2022PDF153.4 KB
FTN324_LAMXO
Rev F16/9/2022PDF140.9 KB
Lattice MachXO Product Family Qualification Summary
Deleted last three pages
H1/23/2015PDF654.9 KB
MN100_XO
Rev Q16/21/2022PDF152.9 KB
MN132_Cu_all
Rev R16/21/2022PDF149.6 KB
TN_TG_TQ144 Cu_wire all
Rev E112/21/2021PDF107.1 KB
TN_TG100 Cu_wire all
Rev D212/21/2021PDF25.4 KB
TN100_LAMXO
Rev B4/19/2018PDF22 KB
TN144_LA
Rev C4/25/2018PDF22.1 KB
TITLENUMBERVERSIONDATEFORMATSIZE
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Creating An ADC Using FPGA Resources
1.03/1/2010PDF272.2 KB
Dual Sensor Design Solution - White Paper (Chinese Language Version)
1.05/31/2012PDF236.6 KB
Expanding Microprocessor Connectivity Using Low-cost FPGAs
1.08/28/2013PDF474.4 KB
ispMACH 4000ZE Practical Low Power CPLD Design
8/25/2009PDF136.5 KB
Low Cost Board Layout Techniques for Designing with PLDs in BGA Packages
1.07/1/2010PDF443.6 KB
Low Cost Board Layout Techniques for Designing with PLDs in BGA Packages (Chinese Language)
1.07/1/2010PDF488.5 KB
MachXO PLDs in System Control Designs
1.010/19/2009PDF876.7 KB
MachXO: Optimized Programmable Devices for Bus Interfaces, Bridges and Control
7/1/2005PDF126.7 KB
MachXO: Platform Management Using Low-Cost Non-Volatile PLDs
2/23/2009PDF512.9 KB
MachXO: Platform Management Using Low-Cost Non-Volatile PLDs (Chinese Language)
1.06/8/2009PDF389.2 KB
Pre-tested Design Accelerates Development
1.03/1/2010PDF299.3 KB
Pre-tested Design Accelerates Development (Chinese Language)
1.06/28/2010PDF1.1 MB
Pre-tested Design Accelerates Development (Korean Language)
1.03/1/2010PDF1.4 MB
Pre-tested Design Accelerates Development (Traditional Chinese Language)
1.06/28/2010PDF1.2 MB
The Challenges of Automotive Vision Systems Design
4/1/2007PDF341.5 KB
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[BSDL] LCMXO640C ftBGA 256
1.044/24/2008BSM37.9 KB
[BSDL] LCMXO1200C caBGA 256
1.006/29/2009BSM43.8 KB
[BSDL] LCMXO1200C csBGA 132
1.034/16/2008BSM34.9 KB
[BSDL] LCMXO1200C ftBGA 256
1.024/16/2008BSM44.4 KB
[BSDL] LCMXO1200C TQFP 100
1.024/16/2008BSM32.1 KB
[BSDL] LCMXO1200C TQFP 144
1.034/16/2008BSM35.9 KB
[BSDL] LCMXO1200E caBGA 256
1.006/29/2009BSM43.2 KB
[BSDL] LCMXO1200E csBGA 132
1.034/16/2008BSM34.2 KB
[BSDL] LCMXO1200E ftBGA 256
1.024/16/2008BSM43.7 KB
[BSDL] LCMXO1200E TQFP 100
1.024/16/2008BSM31.4 KB
[BSDL] LCMXO1200E TQFP 144
1.034/16/2008BSM35.3 KB
[BSDL] LCMXO2280C caBGA 256
1.006/29/2009BSM48.1 KB
[BSDL] LCMXO2280C csBGA 132
1.034/16/2008BSM39.2 KB
[BSDL] LCMXO2280C ftBGA 256
1.034/16/2008BSM48.8 KB
[BSDL] LCMXO2280C ftBGA 324
1.034/16/2008BSM54.2 KB
[BSDL] LCMXO2280C TQFP 100
1.034/16/2008BSM36.5 KB
[BSDL] LCMXO2280C TQFP 144
1.034/16/2008BSM40.3 KB
[BSDL] LCMXO2280E caBGA 256
1.006/29/2009BSM47.6 KB
[BSDL] LCMXO2280E csBGA 132
1.034/16/2008BSM38.5 KB
[BSDL] LCMXO2280E ftBGA 256
1.034/16/2008BSM48.1 KB
[BSDL] LCMXO2280E ftBGA 324
1.034/16/2008BSM53.5 KB
[BSDL] LCMXO2280E TQFP 100
1.034/16/2008BSM35.8 KB
[BSDL] LCMXO2280E TQFP 144
1.034/16/2008BSM39.6 KB
[BSDL] LCMXO256C csBGA 100
1.044/16/2008BSM23 KB
[BSDL] LCMXO256C TQFP 100
1.044/16/2008BSM23 KB
[BSDL] LCMXO256E csBGA 100
1.044/16/2008BSM22.3 KB
[BSDL] LCMXO640C caBGA 256
1.006/29/2009BSM36.9 KB
[BSDL] LCMXO640C csBGA 100
1.044/16/2008BSM28.7 KB
[BSDL] LCMXO640C csBGA 132
1.044/16/2008BSM31.1 KB
[BSDL] LCMXO640C fpBGA 256
1.044/16/2008BSM37.8 KB
[BSDL] LCMXO640C TQFP 100
1.044/16/2008BSM28.7 KB
[BSDL] LCMXO640C TQFP 144
1.044/16/2008BSM32.1 KB
[BSDL] LCMXO640E caBGA 256
1.006/29/2009BSM36.3 KB
[BSDL] LCMXO640E csBGA 100
1.044/16/2008BSM28 KB
[BSDL] LCMXO640E csBGA 132
1.044/16/2008BSM30.5 KB
[BSDL] LCMXO640E fpBGA 256
1.044/16/2008BSM37.1 KB
[BSDL] LCMXO640E ftBGA 256
1.044/24/2008BSM37.1 KB
[BSDL] LCMXO640E TQFP 100
1.044/16/2008BSM28 KB
[BSDL] LCMXO640E TQFP 144
1.044/16/2008BSM31.5 KB
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XO Device Family DELPHI Models
1.09/3/2009ZIP318.3 KB
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[IBIS] Lattice MachXO
2.29/1/2009IBS25.5 MB
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BGA Breakout and Routing Example #1 - BN256
TN10741.012/29/2009ZIP926.8 KB
BGA Breakout and Routing Example #1 - MN100
TN10741.012/29/2009ZIP1.1 MB
BGA Breakout and Routing Example #1 - MN132
TN10741.012/29/2009ZIP803.6 KB
BGA Breakout and Routing Example #2 - BN256
TN10741.012/29/2009ZIP791.8 KB
BGA Breakout and Routing Example #2 - MN100
TN10741.012/29/2009ZIP719.4 KB
BGA Breakout and Routing Example #2 - MN132
TN10741.012/29/2009ZIP804.3 KB
MachXO 2280 Breakout Board Evaluation Kit - OrCAD Capture Schematic Source
Design Entry (.dsn) format schematics for the MachXO 2280 Breakout Board.
1.03/21/2011DSN474.5 KB
MachXO 2280 Breakout Board PCB Artwork
PCB Design (.brd) format PCB artwork and PDF for the MachXO 2280 Breakout board.
1.03/21/2011ZIP3.5 MB
POWR1014A Breakout Board OrCAD Schematic Source
Design Entry (.dsn) format schematics for the POWR1014A Breakout Board.
1.03/21/2011DSN302 KB
POWR1014A Breakout Board PCB Artwork
PCB Design (.brd) format PCB artwork and PDF for the POWR1014A Breakout board.
1.03/21/2011ZIP3.6 MB

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