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ispMACH 4000ZE

Ultra low power, high performance

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High performance, maximum flexibility – The ispMACH4000ZE family integrates up to 256 macrocells that support individual clock reset, preset and clock enable controls that operate at frequencies of up to 260 MHz.

Guard against power drain – Reduce dynamic power consumption to as low as 10 μA by using Power Guard to selectively disable inputs. Reduce system power with per pin pull-up, pull-down or bus keeper control.

Simplify system integration – With flexible multi-volt IOs that support LVCMOS 3.3, LVTTL and PCI and multiple temperature range support, integration into both commercial and industrial designs couldn’t be easier.

Features

  • Ultra low power with standby current as low as 10 μA
  • 5 V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces
  • JTAG In-System Programmable (ISP™)
  • Available in TQFP, csBGA and ucBGA packages
  • Multiple temperature range support: Commercial 0 to 90°C junction (Tj), Industrial -40 to 105°C junction (Tj)

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ispMACH 4000ZE (1.8 V) Device Selection Guide

Parameters 4032ZE 4064ZE 4128ZE 4256ZE
Density Macrocells 32 64 128 256
tpd (ns) 4.4 4.7 5.8 5.8
tco (ns) 3.0 3.2 3.8 3.8
ts (ns) 2.2 2.5 2.9 2.9
fMAX (MHz) 260 241 200 200
Supply Voltage (V) ZE=1.8 ZE=1.8 ZE=1.8 ZE=1.8
I/O Standard Support LVTTL, LVCMOS3.3/2.5/1.8/1.5, PCI3.3
Embedded Oscillator Yes Yes Yes Yes
5 V Tolerant I/Os Yes Yes Yes Yes
Typical Standby Current (µA) 10 11 12 13
Temperature Grades C/I C/I C/I C/I
0.4 mm Spacing I/O Count + Inputs
  4032ZE 4064ZE 4128ZE 4256ZE
64 ucBGA (4 x 4 mm) 48 + 4
132 ucBGA (6 x 6 mm) 96 + 4
0.5 mm Spacing I/O Count + Inputs
  4032ZE 4064ZE 4128ZE 4256ZE
48 TQFP (7 x 7 mm) 32 + 4 32 + 4
100 TQFP (14 x 14 mm) 64 + 10 64 + 10 64 + 10
144 TQFP (20 x 20 mm) 96 + 4 96 + 14
64 csBGA (5 x 5 mm) 32 + 4 48 + 4
144 csBGA (7 x 7 mm) 64 + 10 96 + 4 108 + 4

Design Resources

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Development Kits & Boards

Our development boards & kits help streamline your design process

Complete Design Flows, High Ease of Use

Programming Hardware

Take the strain out of in-system programming & in-circuit reconfiguration with our programming hardware

Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLENUMBERVERSIONDATEFORMATSIZE
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Advanced Features of the ispMACH 4000ZE Family
TN117401.14/29/2008PDF235.5 KB
ispMACH 4000 Timing Model Design and Usage Guidelines
TN10049/1/2001PDF63.4 KB
ispMACH 4000ZE Timing Model Design and Usage Guidelines
TN116801.11/20/2010PDF108.6 KB
Lattice OrCAD Capture Schematic Library
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.		FPGA-SC-020059.012/16/2025ZIP3.2 MB
Package Diagrams
FPGA-DS-020538.58/5/2025PDF9.4 MB
Power Decoupling and Bypass Filtering for Programmable Devices
FPGA-TN-021151.11/26/2022PDF708.9 KB
Power Estimation in ispMACH 4000ZE Devices
TN118701.08/18/2008PDF59.9 KB
SPI Flash Programming and Hardware Interfacing Using ispVM System
TN10813/2/2005PDF685.9 KB
SPI Flash Programming and Hardware Source Archive
TN10813/2/2005ZIP1.8 KB
Thermal Management
FPGA-TN-020445.812/11/2025PDF1.1 MB
USB Programming and Circuit Guide
FPGA-AN-020151.21/22/2021PDF1.4 MB
Using a Discrete Crystal as a PLD Clock Source
FPGA-AN-020161.16/21/2021PDF672.5 KB
Using ispMACH 4000 Devices in Multiple JTAG Voltage Environments
TN10194/1/2002PDF460.1 KB
Using Multiple Boundary Scan Port Linker (BSCAN2)
FPGA-AN-020171.11/9/2022PDF774.3 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

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Die Sale Datasheet
DS10511.03/2/2015PDF731.3 KB
ispMACH 4000ZE Family Data Sheet
DS10221.910/29/2015PDF4.7 MB
TITLENUMBERVERSIONDATEFORMATSIZE
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Advanced Features of the ispMACH 4000ZE Family
TN117401.14/29/2008PDF235.5 KB
ispMACH 4000 Timing Model Design and Usage Guidelines
TN10049/1/2001PDF63.4 KB
ispMACH 4000ZE Timing Model Design and Usage Guidelines
TN116801.11/20/2010PDF108.6 KB
Power Decoupling and Bypass Filtering for Programmable Devices
FPGA-TN-021151.11/26/2022PDF708.9 KB
Power Estimation in ispMACH 4000ZE Devices
TN118701.08/18/2008PDF59.9 KB
SPI Flash Programming and Hardware Interfacing Using ispVM System
TN10813/2/2005PDF685.9 KB
SPI Flash Programming and Hardware Source Archive
TN10813/2/2005ZIP1.8 KB
Thermal Management
FPGA-TN-020445.812/11/2025PDF1.1 MB
USB Programming and Circuit Guide
FPGA-AN-020151.21/22/2021PDF1.4 MB
Using a Discrete Crystal as a PLD Clock Source
FPGA-AN-020161.16/21/2021PDF672.5 KB
Using ispMACH 4000 Devices in Multiple JTAG Voltage Environments
TN10194/1/2002PDF460.1 KB
Using Multiple Boundary Scan Port Linker (BSCAN2)
FPGA-AN-020171.11/9/2022PDF774.3 KB
TITLENUMBERVERSIONDATEFORMATSIZE
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Package Diagrams
FPGA-DS-020538.58/5/2025PDF9.4 MB
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ispMACH 4256ZE Breakout Board Evaluation Kit User's Guide
EB6501.13/26/2012PDF2.3 MB
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Advanced SDR SDRAM Controller - Design Documentation
FPGA-RD-020874.91/22/2021PDF1.1 MB
Advanced SDR SDRAM Controller - Source Code
RD10104.89/12/2014ZIP495.7 KB
Arbitration and Switching Between Bus Masters - Documentation
FPGA-RD-021041.21/21/2021PDF952.5 KB
Arbitration and Switching Between Bus Masters - Source code
RD10671.12/22/2010ZIP284 KB
BSCAN1 - Multiple Boundary Scan Port Addressable Buffer - Documentation
FPGA-RD-021057.41/29/2021PDF993.7 KB
BSCAN1 - Multiple Boundary Scan Port Addressable Buffer - Source Code
RD10017.34/18/2011ZIP152.4 KB
BSCAN2 - Multiple Boundary Scan Port Linker - Source Code
RD10024.63/13/2014ZIP2.6 MB
BSCAN2 - Multiple Scan Port Linker - Documentation
FPGA-RD-021064.91/29/2021PDF918.1 KB
Fast Page Mode SDRAM Controller - Documentation
FPGA-RD-020902.41/22/2021PDF887.1 KB
Fast Page Mode SDRAM Controller - Source Code
RD10142.311/8/2010ZIP110.4 KB
GPIO Expander, Documentation
RD10651.34/12/2011PDF280.6 KB
GPIO Expander, Source Code
RD10651.34/12/2011ZIP195.5 KB
HDLC Controller Implemented in ispMACH 4000ZE and CPLD Families - Documentation
Also download the source code below		RD100903.17/1/2009PDF566 KB
HDLC Controller Implemented in ispMACH 4000ZE and CPLD Families - Source Code
RD10093.17/15/2009ZIP731.5 KB
I2C (Inter-Integrated Circuit) Master Controller - Documentation
RD10055.83/6/2014PDF987.4 KB
I2C (Inter-Integrated Circuit) Master Controller - Source Code
RD10055.91/10/2015ZIP809.7 KB
I2C (Inter-Integrated Circuit) Slave/Peripheral - Documentation
RD10541.612/1/2014PDF801.5 KB
I2C (Inter-Integrated Circuit) Slave/Peripheral - Source Code
RD10541.612/12/2014ZIP764.8 KB
I2C Controller for Serial EEPROMs - Documentation
RD10062.63/5/2014PDF767.9 KB
I2C Controller for Serial EEPROMs - Source Code
RD10062.71/12/2015ZIP613.5 KB
ispMACH 4256ZE Breakout Board Evaluation Kit Source
This demo includes the ispLEVER Classic project source for the preprogrammed demonstration. It programs the LC4256ZE-TN144C with a counter circuit using the embedded oscillator timer and I/O buffers configured for LED drive.		1.03/21/2011ZIP75.7 KB
LED/OLED Driver - Documentation
RD11031.13/1/2014PDF989.6 KB
LED/OLED Driver - Source code
RD11031.13/1/2014ZIP1.4 MB
LPC (Low Pin Count) Bus Controller - Source Code
RD10491.64/12/2011ZIP517.2 KB
LPC (Low Pin Count) Bus Controller Reference Design - Documentation
FPGA-RD-021141.71/21/2021PDF1 MB
PCI Target 32-bit/33MHz
FPGA-RD-021343.61/31/2021PDF1.8 MB
PWM Fan Controller
RD10601.69/10/2014PDF481.5 KB
Read and Write Usercode - Documentation
RD10411.49/17/2014PDF831.5 KB
Read and Write Usercode - Source Code
RD10411.33/1/2014ZIP618.2 KB
Serial Peripheral Interface (SPI) - Documentation
RD10751.112/23/2011PDF158.7 KB
Serial Peripheral Interface (SPI) - Source Code
RD10751.112/23/2011ZIP124.8 KB
SPI GPIO Expander - Documentation
RD10731.112/23/2010PDF212.5 KB
SPI GPIO Expander - Source Code
RD10731.112/23/2010ZIP161.6 KB
SPI WISHBONE Controller - Documentation
RD10441.73/1/2014PDF960 KB
SPI WISHBONE Controller - Source Code
RD10441.81/12/2015ZIP477.7 KB
UART (Universal Asynchronous Receiver/Transmitter) - Source Code
7/15/2025ZIP772.5 KB
Wake on LAN - Documentation
RD10961.06/24/2010PDF311.6 KB
Wake on LAN - Source Code
RD10961.06/24/2010ZIP283.1 KB
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ACN03D-11 Withdrawal of ACN03C-11
Material Set		ANC03D-1114/1/2011PDF796.6 KB
PCN 03C13 Alternate Qualified Assembly Test Site Alternate Qualified Material Sets ASE Taiwan
Assembly Site, Material Set		PCN03C1.011/14/2014PDF212.8 KB
PCN 04A-12 - Revision to ispMACH 4000ZE Data Sheet
Data Sheet		PCN04A-121.02/27/2012PDF50.7 KB
PCN 04A-12 Affected Devices List
PCN04A-122/24/2012XLSX25 KB
PCN 09A-12 Affected Devices
Assembly Site		PCN09A-121.05/14/2012XLSX121 KB
PCN 09A-12 Alternate Qualified Material Set, Assembly Site for Select Lattice Families
PCN09A-121.05/14/2012PDF160.2 KB
PCN 09A-12 Frequently Asked Questions
PCN09A-121.05/11/2012PDF178.9 KB
PCN 09A-12 Material Set Changes
Assembly Site		PCN09A-121.05/14/2012XLSX121 KB
PCN03A-13 Alternate Qualified Assembly and Material Sets for Select Devices
PCN03A-136/28/2013PDF202.5 KB
PCN03A-13 Device Characterization Report
PCN03A-136/28/2013PDF981.3 KB
PCN03A-13 FAQs
PCN03A-136/28/2013PDF458.3 KB
PCN03A-14 Characterization Report
PCN03A-141.04/4/2014PDF919.5 KB
PCN03A-14 FAQ
PCN03A-141.04/4/2014PDF452.5 KB
PCN03A-14 Material Set Table
PCN03A-141.04/4/2014XLSX26.9 KB
PCN03B-14 Notification of Intent to Utilize an Alternate Qualified Assembly Site/Test Site and/or Alternate Qualified Material Sets for Select Lattice Products
PCN03B-141.011/21/2014PDF229.9 KB
PCN03C-13 Affected Part Number and Material Sets
PCN03C-136/28/2013XLSX51.2 KB
PCN03C-14 Affected Part Number List
PCN03C-141.04/4/2014XLSX50.8 KB
PCN04B-11 Alternate Qualified Mask Set and Foundry for ispMACH 4000ZE
Mask Set		PCN04B-111.07/21/2011PDF68.1 KB
PCN05A-17 Affected Parts List
1.010/18/2017XLSX14.9 KB
PCN05A-17 Halogen-Free substrate at ASEM
1.210/27/2017PDF268 KB
PCN06A-14 Characterization Report
PCN06A-141.010/3/2014PDF563.7 KB
PCN06A-14 Material Set Table
PCN06A-141.010/3/2014XLSX13.7 KB
PCN06B-14 Notification of Intent to Utilize an Alternate Qualified Assembly Site/Test Site and Alternate Qualified Material Sets for Select Lattice Products
PCN06B-141.011/21/2014PDF229.5 KB
PCN06C-11 Withdrawal of PCN06B-11
Material Set		PCN06C-111.08/1/2011PDF838.5 KB
PCN06C-14 Affected Device List
PCN06C-141.010/3/2014XLSX29.6 KB
PCN07C-11 Withdrawal of PCN07B-11
Material Set		PCN07C-111.08/1/2011PDF917.9 KB
PCN08A13_AffectedDevices
Other		PCN08A-1319/26/2013XLSX78.2 KB
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Lattice OrCAD Capture Schematic Library
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.		FPGA-SC-020059.012/16/2025ZIP3.2 MB
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Automotive Solutions Product Brief
I01648.06/5/2009PDF2.4 MB
ispMACH 4000ZE Pico Development Kit Product Brief
I02041.05/22/2013PDF1 MB
ispMACH 4000ZE Product Brief
I01967.04/30/2010PDF1.1 MB
ispMACH 4000ZE Product Brief (Chinese)
I0196C8.011/19/2012PDF1.8 MB
ispMACH 4000ZE Product Brief (Japanese)
I0196J7.09/28/2010PDF991 KB
Lattice FPGA Product Selector Guide
v25.3.01/6/2026PDF717 KB
Ultra-Low Density FPGAs for Handheld Devices Brochure
I022510/22/2012PDF5.8 MB
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Lattice ispMACH4000 V/B/C/ZC/ZE Product Family Qualification Summar
G10/1/2012PDF1.1 MB
MN132_Cu_all
Rev R16/21/2022PDF149.6 KB
MN144_4kZE
Rev R16/21/2022PDF151.9 KB
MN64_4kZE
Rev P16/21/2022PDF147.9 KB
TN_TG_TQ144 Cu_wire all
Rev E112/21/2021PDF107.1 KB
TN_TG100 Cu_wire all
Rev D212/21/2021PDF25.4 KB
TN48_4kZE
Rev D5/2/2018PDF25.3 KB
UMN132_4kZE
Rev Q16/21/2022PDF141.7 KB
UMN64_4kZE
Rev Q16/21/2022PDF141.6 KB
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ispMACH 4000ZE - Enabling CPLDs in Ultra High Volume, Low Power Applications
4/28/2008PDF178.5 KB
ispMACH 4000ZE - Enabling CPLDs in Ultra High Volume, Low Power Applications (Chinese Language)
1.06/8/2009PDF396.3 KB
ispMACH 4000ZE Practical Low Power CPLD Design
8/25/2009PDF136.5 KB
Low Cost Board Layout Techniques for Designing with PLDs in BGA Packages (Chinese Language)
1.07/1/2010PDF488.5 KB
Practical Low Power CPLD Design (Chinese Language)
1.06/28/2010PDF461.6 KB
Practical Low Power CPLD Design (Japanese Language)
1.06/28/2010PDF519.1 KB
Practical Low Power CPLD Design (Korean Language)
5/22/2013PDF541.9 KB
Practical Low Power CPLD Design (Traditional Chinese Language)
5/22/2013PDF551.2 KB
White Paper: The Impact of Energy Efficiency Standards on Standby Power in Consumer Electronics Design
6/7/2010PDF87.1 KB
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[BSDL] ispMACH 4032ZE TQFP 48
1.004/24/2008BSM12.8 KB
[BSDL] ispMACH 4064ZE CSBGA 144
1.004/1/2008BSM18.5 KB
[BSDL] ispMACH 4064ZE CSBGA 64
1.004/28/2008BSM17 KB
[BSDL] ispMACH 4064ZE TQFP 100
1.004/28/2008BSM17.9 KB
[BSDL] ispMACH 4064ZE TQFP 48
1.004/28/2008BSM16.3 KB
[BSDL] ispMACH 4064ZE UCBGA 64
1.004/28/2008BSM17.1 KB
[BSDL] ispMACH 4128ZE CSBGA 144
1.004/28/2008BSM22.3 KB
[BSDL] ispMACH 4128ZE TQFP 100
1.004/28/2008BSM20.9 KB
[BSDL] ispMACH 4128ZE TQFP 144
1.004/28/2008BSM22.2 KB
[BSDL] ispMACH 4128ZE UCBGA 132
1.004/28/2008BSM22.1 KB
[BSDL] ispMACH 4256ZE CSBGA 144
1.004/28/2008BSM25.7 KB
[BSDL] ispMACH 4256ZE TQFP 100
1.004/28/2008BSM24 KB
[BSDL] ispMACH 4256ZE TQFP 144
1.004/28/2008BSM25.7 KB
ispMACH 4032ZE CSBGA 64
BSDL1.017/19/2010BSM13.2 KB
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[IBIS] ispMach 4000ZE
1.112/9/2008IBS578.8 KB
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BGA Breakout and Routing Example - MN64
TN10741.012/29/2009ZIP791.2 KB
BGA Breakout and Routing Example - UMN64
TN10741.012/29/2009ZIP815 KB
BGA Breakout and Routing Example #1 - MN144
TN10741.012/29/2009ZIP920.3 KB
BGA Breakout and Routing Example #2 - MN144
TN10741.012/29/2009ZIP964 KB
ispMACH 4256ZE Breakout Board OrCAD Capture Schematic Source
Design Entry (.dsn) format schematics for the ispMACH 4256ZE Breakout Board.		1.03/21/2011DSN384.5 KB
ispMACH 4256ZE Breakout Board PCB Artwork
PCB Design (.brd) format PCB artwork and PDF for the ispMACH 4256ZE Breakout board.		1.03/21/2011ZIP3.9 MB

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